tangxifan
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7f75c2b619
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[Test] Deploy shift register -based QL memory bank test case to basic regression test
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2021-10-03 16:06:44 -07:00 |
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tangxifan
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86e7c963f8
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[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
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2021-10-02 22:19:20 -07:00 |
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tangxifan
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0b06820177
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[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
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2021-10-01 17:06:35 -07:00 |
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tangxifan
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7ba5d27ea7
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[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
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2021-10-01 17:02:35 -07:00 |
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tangxifan
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ff6f7e80f6
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[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
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2021-10-01 16:52:06 -07:00 |
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tangxifan
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dda147e234
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[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
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tangxifan
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7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
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tangxifan
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fa57117f50
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[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
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2021-10-01 10:19:51 -07:00 |
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tangxifan
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41cc375746
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[Arch] define default CCFF model in ql bank example architecture that uses shift registers
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2021-09-29 16:34:40 -07:00 |
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tangxifan
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89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
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4968f0d11f
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Merge branch 'master' into qlbank_sr
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2021-09-28 14:20:30 -07:00 |
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tangxifan
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80232fc459
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[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
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2021-09-28 12:36:36 -07:00 |
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tangxifan
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4c04c0fbd7
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[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
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2021-09-28 12:35:42 -07:00 |
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tangxifan
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2ce2fb269a
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[HDL] Added a different FF model which is designed to drive WLW only
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2021-09-28 12:35:13 -07:00 |
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tangxifan
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6469ee3048
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[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
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2021-09-28 12:21:54 -07:00 |
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tangxifan
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4400dae108
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[Test] Bug fix in the wrong arch name
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2021-09-28 11:40:25 -07:00 |
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tangxifan
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4aed045cdd
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[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
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2021-09-28 11:34:20 -07:00 |
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tangxifan
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811c898173
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[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
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2021-09-28 11:29:45 -07:00 |
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tangxifan
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dae3554fd4
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[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
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tangxifan
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1ca1b0f3e9
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[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
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2021-09-22 15:58:05 -07:00 |
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tangxifan
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655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
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a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
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53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
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3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
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212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
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b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
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efed268585
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[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
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2021-09-22 11:30:08 -07:00 |
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tangxifan
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abfa380333
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[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
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337ed33b68
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[Test] Added a sample fabric key for 2-region QL memory bank
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2021-09-22 11:25:16 -07:00 |
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tangxifan
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7db7e2d8f6
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[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
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2021-09-22 10:05:27 -07:00 |
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tangxifan
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d0fe12fadd
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[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
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51fc222d61
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[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
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ab42239b94
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[Test] Bug fix in the fabric key
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2021-09-21 16:44:58 -07:00 |
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tangxifan
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f57aceff87
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[Test] Deploy the load external key test case for ql memory bank to basic regression tests
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2021-09-21 16:25:14 -07:00 |
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tangxifan
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aad47ffbc6
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[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
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2021-09-21 16:22:50 -07:00 |
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tangxifan
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1412121541
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[Test] Added a new test to validate the fabric key parser for QL memory bank
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2021-09-21 16:20:24 -07:00 |
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tangxifan
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cd0d8b86fa
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[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
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2021-09-21 15:55:34 -07:00 |
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tangxifan
|
7327850cf3
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[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
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2021-09-21 15:43:54 -07:00 |
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tangxifan
|
dc2d1d1c3c
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[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
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2021-09-21 15:42:20 -07:00 |
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tangxifan
|
d36d1ebee2
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[HDL] Temporarily disable WLR func in primitive HDL modeling
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2021-09-20 17:07:51 -07:00 |
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tangxifan
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0450d57d82
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[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
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2021-09-20 16:05:01 -07:00 |
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tangxifan
|
3f6ac41868
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[Test] Deploy the WLR test to the basic regression tests
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2021-09-20 11:21:58 -07:00 |
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tangxifan
|
60fc3ab36c
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[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
|
5c1c428ea5
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[HDL] Updated cell library with the SRAM cell with Read Enable signal
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2021-09-20 11:13:36 -07:00 |
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tangxifan
|
cd2978a434
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[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
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2021-09-20 11:13:02 -07:00 |
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tangxifan
|
81a2ad58df
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[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
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2021-09-09 13:48:30 -07:00 |
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tangxifan
|
b82cfdf555
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[Test] Add the QL memory bank test to regression test cases
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2021-09-09 09:29:21 -07:00 |
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tangxifan
|
6be3c64f1c
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[Arch] Add an example architecture using the physical design friendly memory bank organization
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2021-09-09 09:22:27 -07:00 |
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tangxifan
|
6adf439081
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Merge remote-tracking branch 'upstream/master'
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2021-09-01 14:19:00 -07:00 |
Will
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c31c1d8b04
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Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
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2021-08-13 11:08:09 -04:00 |