tangxifan
|
286df30947
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[test] update clock arch xml syntax
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2024-06-29 11:02:17 -07:00 |
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tangxifan
|
4f787a5cfc
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[core] add more debugging message
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2024-06-29 10:54:08 -07:00 |
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tangxifan
|
5fa674be24
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[core] fixed the bug on matching global net from pcf
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2024-06-29 10:51:45 -07:00 |
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tangxifan
|
34fb003911
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[core] replace width syntax with global port name
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2024-06-29 10:46:00 -07:00 |
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tangxifan
|
67554cb8d8
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[test] now use correct pcf for clock network testcases
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2024-06-29 10:04:03 -07:00 |
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tangxifan
|
8bc37080fa
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[core] debuggging
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2024-06-28 23:06:21 -07:00 |
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tangxifan
|
1c69365938
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[core] debugging
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2024-06-28 18:17:38 -07:00 |
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tangxifan
|
0de3ff3eb8
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[core] debugging
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2024-06-28 17:16:33 -07:00 |
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tangxifan
|
e0b9f7860b
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[core] fixed a bug where counter for gnets are not activated
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2024-06-28 14:10:14 -07:00 |
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tangxifan
|
5cfd23747b
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[core] code format
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2024-06-28 13:47:03 -07:00 |
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tangxifan
|
f4dd222c47
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[test] deploy new testcases to basic reg tests
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2024-06-28 13:45:36 -07:00 |
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tangxifan
|
f1a4304ee7
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[test] add new testcases for validate clock tree disable functions
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2024-06-28 13:43:53 -07:00 |
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tangxifan
|
ad5795bece
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[test] add extra options to route clock rr_graph command in examples
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2024-06-28 13:39:41 -07:00 |
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tangxifan
|
1094af9f73
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[doc] add new options to route clock graph
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2024-06-28 12:38:40 -07:00 |
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tangxifan
|
f5b6774eb0
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[core] add code comments and fixed some bugs
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2024-06-28 12:21:33 -07:00 |
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tangxifan
|
53ba2f0c29
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[core] fixed a critical bug where some switching points are missing
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2024-06-27 15:53:17 -07:00 |
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tangxifan
|
5a7f618f29
|
[core] debugging
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2024-06-27 15:44:17 -07:00 |
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tangxifan
|
f4f487099d
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[core] syntax
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2024-06-27 15:07:48 -07:00 |
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tangxifan
|
4185235a69
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[core] now clock routing is based on tree expansion. Unused part can be disconnected
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2024-06-27 15:02:20 -07:00 |
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tangxifan
|
e75fd57af2
|
[core] refactor codes
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2024-06-27 12:39:18 -07:00 |
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tangxifan
|
7892c2340c
|
[core] add a new option 'disable_unused_trees' to route clock rr graph
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2024-06-27 12:01:54 -07:00 |
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tangxifan
|
3fb891094b
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[doc] add new syntax
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2024-06-27 11:02:37 -07:00 |
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tangxifan
|
6fceb81110
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[core] code format
|
2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
|
2024-06-27 10:19:14 -07:00 |
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tangxifan
|
9ce552495a
|
[core] now internal drivers can be routed in dedicated clock network
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2024-06-27 10:17:08 -07:00 |
|
tangxifan
|
ac1ad52795
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[core] code format
|
2024-06-26 22:47:29 -07:00 |
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tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
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2024-06-26 22:46:12 -07:00 |
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tangxifan
|
d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
|
2024-06-26 21:52:45 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
|
tangxifan
|
59404e5487
|
[core] add verbose output
|
2024-06-26 17:55:23 -07:00 |
|
tangxifan
|
576a861b8d
|
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
|
2024-06-26 17:54:31 -07:00 |
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tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
3b25e42720
|
[lib] syntax
|
2024-06-26 15:51:00 -07:00 |
|
tangxifan
|
381a8cb535
|
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
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2024-06-26 15:41:56 -07:00 |
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tangxifan
|
ec1ad94d4a
|
[doc] add syntax about internal drivers
|
2024-06-25 13:06:47 -07:00 |
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tangxifan
|
c99178f350
|
[test] fixed a bug on pin locations
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2024-06-25 12:34:52 -07:00 |
|
tangxifan
|
4640e74e7e
|
[core] code format
|
2024-06-25 12:25:16 -07:00 |
|
tangxifan
|
66af73e91e
|
[lib] now accept reset and set in programmable clock network
|
2024-06-25 12:24:46 -07:00 |
|
tangxifan
|
fbece49047
|
[core] fixed a bug where unexpected OPINs are added as internal drivers
|
2024-06-25 12:07:19 -07:00 |
|
tangxifan
|
2cbb04b90d
|
[test] add a new testcase to validate programmable clock network with internal drivers
|
2024-06-25 11:58:05 -07:00 |
|
tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
|
tangxifan
|
272d78eb43
|
[test] add a new unit test
|
2024-06-24 19:13:36 -07:00 |
|
tangxifan
|
22bee35fd1
|
[lib] mem allocate
|
2024-06-24 18:47:56 -07:00 |
|
tangxifan
|
36ef555dda
|
[lib] add example arch for clock arch with internal drivers
|
2024-06-24 18:33:47 -07:00 |
|
tangxifan
|
2eda2825b7
|
[lib] syntax
|
2024-06-24 18:28:42 -07:00 |
|
tangxifan
|
0c442f6238
|
[lib] add syntax to support internal drivers in clock network parsers
|
2024-06-24 17:54:58 -07:00 |
|
tangxifan
|
582efc0501
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2
|
2024-06-24 10:42:29 -07:00 |