ff7ea99381
bug fixed in register scan-chain architecture
2020-04-07 17:06:16 -06:00
2342d7cdc6
minor tweak on the scan-chain support in VPR8 as well as architecture file
...
Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
2020-04-07 17:03:44 -06:00
50bb04d496
add scan-chain test case. Debugging on the way
2020-04-07 16:50:41 -06:00
6daee8c2c8
bug fixed in the example architecture
2020-04-07 16:03:34 -06:00
628ea3b654
improve adder chain arch XML to support sequential output for sumout
2020-04-07 15:39:37 -06:00
26d1261c1f
add test cases using shift registers
2020-04-07 15:09:10 -06:00
13cd48c119
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
32c74ad811
added FPGA architecture with I/Os on the left and right sides
2020-04-01 15:46:38 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
34a1b61ecb
add an example FPGA architecture with AIB interface at the right side of I/Os
2020-03-27 18:45:27 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
b09b051249
add all the test cases considering tileable, carry chain, direct connection and memory blocks
2020-03-27 13:58:35 -06:00
e47a0a4422
add through channel architecture example
2020-03-27 11:32:44 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
610c71671f
experimentally developing through channels inside multi-width and multi-height grids.
...
Still debugging.
2020-03-24 16:47:45 -06:00
8a996ceae5
bug fixed in tileable routing when heterogeneous blocks are considered;
...
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
08b46af7be
add micro architecture for heterogeneous FPGA with single-mode DPRAM
2020-03-24 12:20:51 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
fc6abc13fd
add physical tile utils to identify pins that have Fc=0
2020-03-21 21:02:47 -06:00
637be076dc
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
2020-03-21 18:49:20 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
63c4669dbb
fixed bug in the fast look-up for tileable rr_graph
2020-03-21 17:36:08 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
2ff2d65e58
start debugging tileable routing using larger array size. Bug spotted in finding chan nodes
2020-03-20 22:12:23 -06:00
3c37b33f17
critical bug fixed in edge sorting for rr_gsb
2020-03-20 17:45:50 -06:00
708fda9606
fixed a bug in using tileable routing when directlist is enabled
2020-03-20 16:38:58 -06:00
c5049a1ec8
keep debugging tile direct connections
2020-03-20 15:10:00 -06:00
9837be618d
start debugging tile direct with micro architecture
2020-03-20 14:52:52 -06:00
a0b150f12e
adding micro architecture using adder chain
2020-03-20 14:18:59 -06:00
f90dc5c296
remove redundant XML codes
2020-03-12 20:44:07 -06:00
5be118d695
tileable rr_graph builder ready to debug
2020-03-06 16:18:45 -07:00
80bb2baae5
start verification and bug fixing
2020-02-28 14:29:01 -07:00
1b66e837ba
bug fixing for lb router. Add physical mode to default node expanding settings
2020-02-21 11:29:00 -07:00
0b0e00b5f4
debugging the LbRouter
2020-02-20 21:56:15 -07:00
4a05cec037
add rr_segment binding to circuit model
2020-02-12 11:21:40 -07:00
02d6256e95
pass simple test on pb_type annotation for frac_lut5 architecture
2020-01-30 21:39:44 -07:00
01c80b9126
add sample architecture to be used for Openfpga
2020-01-27 13:39:13 -07:00
tangxifan