tangxifan
|
3bf94b8e34
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[Regression test] Remove no local routing from fpga verilog tests
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2020-09-22 11:48:19 -06:00 |
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tangxifan
|
7ed9f76b06
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[Regression test] Move k4n4 no local routing to basic test
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2020-09-22 11:47:03 -06:00 |
|
tangxifan
|
2dea97afb6
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[Regression test] reduce runtime for k4n4 test in basic testing
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2020-09-22 11:45:29 -06:00 |
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tangxifan
|
ea4dd410b7
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[Regression Test] Add k4n4 fracturable lut test case to basic test
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2020-09-22 11:41:36 -06:00 |
|
tangxifan
|
dad19cac9a
|
[Regression test] Add k4 series architecture: fracturable adder
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2020-09-22 11:39:18 -06:00 |
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tangxifan
|
dd192a2f54
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[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
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2020-09-22 11:34:23 -06:00 |
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tangxifan
|
7a6f5a06f7
|
[Architecture] Add a k4n4 architecture with carry chain to quick test
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2020-09-22 11:33:56 -06:00 |
|
tangxifan
|
aa5f5fc7e0
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[Architecture] Bring back pin equivalence for no local routing architecture
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2020-09-21 22:22:39 -06:00 |
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tangxifan
|
a8a269aa82
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[Architecture] Temporary patch for the no local routing architecture
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2020-09-21 19:51:23 -06:00 |
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tangxifan
|
acf318f184
|
[Regression test] Bug fix in test case fabric_chain
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2020-09-21 18:58:35 -06:00 |
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tangxifan
|
e4291eb27e
|
[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
|
7a57cc9cf4
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[Architecture] A new device layout to k4n4 to test untileable architecture
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2020-09-21 18:36:50 -06:00 |
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tangxifan
|
2bbfcb5753
|
[Architecture] Add a new device layout to k4n4 for testing tileable routing
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2020-09-21 18:34:31 -06:00 |
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tangxifan
|
e1c5947143
|
[Architecture] Add auto layout and fixed layout to architectures
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2020-09-21 18:01:51 -06:00 |
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tangxifan
|
936a164eee
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[OpenFPGA flow] Add a new template script to use a fixed device layout
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2020-09-21 17:48:28 -06:00 |
|
tangxifan
|
d7f8b3abad
|
[Architecture] Add k4 N4 untilable architecture
|
2020-09-21 17:44:37 -06:00 |
|
tangxifan
|
a83bc3f75c
|
[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
|
tangxifan
|
e9c0e90544
|
[Architecture] Add a VPR architectue using fracturable LUT4
|
2020-09-21 17:37:26 -06:00 |
|
tangxifan
|
60f328a2ab
|
[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
|
2020-09-21 17:36:57 -06:00 |
|
tangxifan
|
681e80d4b6
|
[Regression tests] update frac_lut test case using more representative benchmarks
|
2020-09-17 10:39:22 -06:00 |
|
tangxifan
|
367cf59efd
|
[Benchmark] Bug fix in the and2_or2 benchmark
|
2020-09-17 10:35:13 -06:00 |
|
tangxifan
|
de48b8c7b2
|
[Benchmark] Add a new micro benchmark to test fracturable LUTs
|
2020-09-17 10:21:25 -06:00 |
|
tangxifan
|
ca1bafc688
|
[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
|
2020-09-16 19:26:12 -06:00 |
|
tangxifan
|
c22d8e2421
|
[Architecture] Bug fix in no local routing architecture
|
2020-09-16 18:07:52 -06:00 |
|
tangxifan
|
c40c9f5876
|
[Regression test] add test case for no local routing architecture
|
2020-09-16 18:05:33 -06:00 |
|
tangxifan
|
f5b7ac6269
|
[OpenFPGA Architecture] Add a new architecture with no local routing
|
2020-09-16 18:04:55 -06:00 |
|
tangxifan
|
35d47ee0e7
|
[Regression tests] bug fix in the test case for fully connected output crossbar
|
2020-09-16 17:33:54 -06:00 |
|
tangxifan
|
030d7f02f8
|
[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
|
2020-09-16 17:30:08 -06:00 |
|
tangxifan
|
30fb99095f
|
[Regression Tests] Add new test case for fully connected output crossbar
|
2020-09-16 17:29:15 -06:00 |
|
tangxifan
|
3c0faf0021
|
[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
|
2020-09-16 17:27:24 -06:00 |
|
tangxifan
|
f42411c29e
|
[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
|
2020-09-14 16:03:43 -06:00 |
|
tangxifan
|
aaf63050bb
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
|
2020-09-14 15:58:34 -06:00 |
|
tangxifan
|
aa9521b23b
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
|
2020-09-14 15:57:44 -06:00 |
|
tangxifan
|
eecfd186f0
|
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
|
2020-09-14 15:46:10 -06:00 |
|
tangxifan
|
9bf0e772a3
|
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
|
2020-09-14 15:45:35 -06:00 |
|
tangxifan
|
4b3142c4ee
|
[Architecture File] Patch openfpga architecture with default circuit model definition
|
2020-08-23 15:13:28 -06:00 |
|
tangxifan
|
9101ba1021
|
[Architecture Language] Update openfpga architecture files for default models
|
2020-08-23 14:55:44 -06:00 |
|
tangxifan
|
6c925dcded
|
[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |
|
tangxifan
|
881672d46a
|
update thru channel arch for avoid buggy pin locations
|
2020-08-19 19:52:35 -06:00 |
|
tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
f0bc6f83f1
|
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
|
2020-08-19 15:34:59 -06:00 |
|
tangxifan
|
18735894f9
|
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
|
2020-08-19 15:27:30 -06:00 |
|
tangxifan
|
3273f441fe
|
bug fix in the flagship vpr arch
|
2020-08-19 15:23:20 -06:00 |
|
tangxifan
|
aa4a9b28cc
|
start testing the initial offset in the flagship architecture
|
2020-08-19 15:03:46 -06:00 |
|
tangxifan
|
f64079641d
|
bug fix in flagship vpr arch with frac mem and dsp
|
2020-08-19 12:43:58 -06:00 |
|
tangxifan
|
d7efdf35b6
|
add custom pin location to the flagship vpr arch with frac mem and dsp
|
2020-08-19 11:15:25 -06:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
tangxifan
|
743167521a
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |
|
tangxifan
|
42b5ea2cb1
|
bug fix in openfpga arch for frac mem and dsp
|
2020-08-18 20:42:36 -06:00 |
|
tangxifan
|
3ee4e10aa8
|
bug fix in the frac mem & DSP vpr arch
|
2020-08-18 17:25:45 -06:00 |