tangxifan
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1f39540672
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update documentation about fabric bitstream file formats
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2020-07-26 21:38:33 -06:00 |
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tangxifan
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80e982fb39
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minor file format fix in fabric bitstream XML
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2020-07-26 21:35:48 -06:00 |
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tangxifan
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b3ad04fd1e
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minor file format fix in fabric bitstream XML
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2020-07-26 21:33:47 -06:00 |
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tangxifan
|
861e346830
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minor bug fix in fabric bitstream XML writer
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2020-07-26 21:31:08 -06:00 |
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tangxifan
|
5fb7d9fbdb
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bug fix in fabric bitstream file format writer
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2020-07-26 21:28:45 -06:00 |
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tangxifan
|
92d2d2d849
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add fabric bitstream XML writer
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2020-07-26 21:00:57 -06:00 |
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tangxifan
|
a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
|
58f7cc9a8c
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deploy FPGA-SPICE test case to CI
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2020-07-24 19:13:32 -06:00 |
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tangxifan
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c87f6b75b9
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add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
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tangxifan
|
f9de802dbd
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deploy depopulated crossbar test case in CI
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2020-07-24 18:07:12 -06:00 |
|
tangxifan
|
020154b0cd
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add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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tangxifan
|
fd3e947c6d
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update FPGA_SPICE to support max width for transistors and multi-bin
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2020-07-24 17:52:31 -06:00 |
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tangxifan
|
c3fd817bae
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update documentation about new XML syntax max width
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2020-07-24 16:33:01 -06:00 |
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tangxifan
|
6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
|
73e2b857a3
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add buffer support to FPGA-SPICE
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2020-07-24 15:54:18 -06:00 |
|
tangxifan
|
021fedbc12
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update fabric key to synchronize with new module/instance naming
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2020-07-24 12:55:40 -06:00 |
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tangxifan
|
2603836111
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split logical tile netlists to keep good Verilog hierarchy
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2020-07-24 12:53:21 -06:00 |
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tangxifan
|
be5966475e
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formulate file name, module name and instance name to be consistent
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2020-07-24 12:23:27 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
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2020-07-22 21:55:59 -06:00 |
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tangxifan
|
8a79ff2c24
|
deploy power gating test cases to CI
|
2020-07-22 20:22:59 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
|
tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
a4a38f8156
|
support multi-bit power gate ports in FPGA-SPICE
|
2020-07-22 20:04:39 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
97cca72590
|
add spice support on power gated inverters
|
2020-07-22 18:21:11 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |
|
tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
|
tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
|
2020-07-22 12:44:19 -06:00 |
|
tangxifan
|
7d39e136a4
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
|
tangxifan
|
1d36de817f
|
adapt generate bitstream testcase to use yosys vpr flow
|
2020-07-22 12:24:34 -06:00 |
|
tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
|
2020-07-22 12:23:39 -06:00 |
|
tangxifan
|
d8804f4ec1
|
deploy yosys_vpr flow to basic regression tests
|
2020-07-22 12:21:59 -06:00 |
|
tangxifan
|
f4e77e3bad
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-22 12:09:34 -06:00 |
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
ganeshgore
|
226f1c703a
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-07-22 11:39:23 -06:00 |
|
tangxifan
|
b5fd6aa859
|
add inverter subckt writer to FPGA-SPICE
|
2020-07-17 13:01:08 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
c26c268dcd
|
update documentation on fast configuration support for configuration chain
|
2020-07-15 13:55:32 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
ffc087336d
|
Merge pull request #68 from LNIS-Projects/dev
Remove obsolete documentation and add technology binding
|
2020-07-15 12:24:50 -06:00 |
|
tangxifan
|
7d1b524969
|
deploy fast configuration chain test case to CI
|
2020-07-15 11:57:12 -06:00 |
|
tangxifan
|
ca90f337a7
|
add fast configuration chain test case
|
2020-07-15 11:56:47 -06:00 |
|
tangxifan
|
66a50742fc
|
use configuration chain in the k4k4 test case to speed up CI
|
2020-07-15 11:56:11 -06:00 |
|
tangxifan
|
3f14fe62c7
|
add fast configuration support for configuration chain protocol
|
2020-07-15 11:44:23 -06:00 |
|
tangxifan
|
862d71f57a
|
remove obselete vpr7 XML syntax from documentation
|
2020-07-15 11:13:47 -06:00 |
|
tangxifan
|
cb0df2c1c6
|
update doc about technology binding between circuit library and device library
|
2020-07-15 11:05:33 -06:00 |
|
tangxifan
|
de4586217f
|
now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |