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OpenFPGA
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76 Commits

Author SHA1 Message Date
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 4add9781d5 [Script] Add a new openfpga shell script for don't care bits outputting 2021-10-05 19:13:50 -07:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00
tangxifan 9655bc35cb [Script] Bug fix due to the full testbench generation changes 2021-06-29 17:04:19 -06:00
tangxifan 20faf82e64 [Script] Rename example script 2021-06-29 16:02:35 -06:00
tangxifan 01391fd81e [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features 2021-06-29 15:56:33 -06:00
tangxifan 4a623bec79 [Script] Add example openfpga shell script to generate preconfigured fabric wrapper 2021-06-27 19:55:40 -06:00
tangxifan fae5e1dfdf [Script] Upgrade openfpga shell script with the new option '--embed_bitstream' 2021-06-25 15:16:37 -06:00
tangxifan b2c30e3103 [Test] Bug fix in mcnc openfpga shell script 2021-06-22 16:40:24 -06:00
tangxifan 96cb3081ab
Update fix_device_route_chan_width_example_script.openfpga 2021-06-18 09:51:16 -06:00
tangxifan d40cf98c48 [Test] Update test cases by using default net type in testbench generator 2021-06-14 11:47:28 -06:00
tangxifan d545069aac [Script] Bug fix 2021-06-09 14:50:37 -06:00
tangxifan 4e3f589810 [Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench' 2021-06-09 13:53:28 -06:00
tangxifan f9404dc97d [Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench' 2021-06-09 11:55:25 -06:00
tangxifan 9adf94bfd3 [Script] Update all the openshell scripts to deprecate 'write_verilog_testbench' 2021-06-09 11:18:52 -06:00
tangxifan be26c06673 [Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench' 2021-06-09 10:41:22 -06:00
tangxifan e9fa44cc25 [Tool] Add fast configuration to the write bitstream command in example shell script 2021-06-04 16:24:56 -06:00
tangxifan f5e90c9467 [Script] Update openfpga shell script with fast configuration option 2021-06-04 11:28:10 -06:00
tangxifan 8fc90637e0 [Script] Update write_full_testbench example script to support custom device layout in VPR 2021-06-03 17:08:08 -06:00
tangxifan 51ca62a464 [Script] Add example script for write_full_testbench command 2021-06-03 15:48:59 -06:00
tangxifan 7dc7c1b4f5 [Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command 2021-05-07 12:05:47 -06:00
tangxifan f9fd444b86 [Script] Add an write I/O mapping example script for openfpga shell 2021-04-27 14:40:26 -06:00
tangxifan 09cc7f0007 [Script] Enable constant net routing for heterogeneous FPGAs 2021-04-23 20:44:36 -06:00
tangxifan cbb7d41b6e [Script] Enable constant net routing for VTR benchmarks 2021-04-23 14:15:13 -06:00
tangxifan a16896054d [Script] Enable constant net routing for iwls benchmarks 2021-04-22 19:16:32 -06:00
tangxifan 64163edbe6 [Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting 2021-04-19 16:15:25 -06:00
tangxifan 7018073e28 [Script] Update openfpga shell script w/o ace usage to adapt pin constraint files 2021-04-17 15:04:51 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan 2666726f36 [Script] Remove clock routing from example openfpga shell script without ace 2021-04-16 20:46:49 -06:00
tangxifan 23d08757cf [Script] Add example script without using ACE2 2021-04-16 20:20:10 -06:00
tangxifan 43bf016576 [Script] Add example openfpga shell script for iwls benchmark 2021-04-16 16:09:47 -06:00
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 07f6066c11 [Script] Update timing unit in SDC example script 2021-04-11 20:24:18 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan 145a80de43 [Script] Add an openfpga shell script for heterogeneous fpga verification 2021-03-23 15:35:34 -06:00
tangxifan d050f1b746 [Script] Enable fast bitstream generation for VTR benchmarks 2021-03-22 12:54:36 -06:00
tangxifan eca2a35612 [Script] Add route chan width option to vtr openfpga script 2021-03-20 22:00:09 -06:00
tangxifan cb07848475 [Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation 2021-03-20 18:11:54 -06:00
tangxifan deee7ba366 [Script] Add example script to run vtr benchmarks 2021-03-17 15:10:56 -06:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00