tangxifan
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07994d424c
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add XML parser and writer for direct connection
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2020-01-19 15:00:19 -07:00 |
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tangxifan
|
10336cbe67
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add XML parser and writer for routing circuit definition for OpenFPGA architecture
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2020-01-19 14:44:27 -07:00 |
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tangxifan
|
ebe46d15a9
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add XML parser, writer and linker for configuration protocol data structure
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2020-01-18 21:19:20 -07:00 |
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tangxifan
|
9693c3a12d
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add XML writer for simulation setting object
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2020-01-18 16:41:42 -07:00 |
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tangxifan
|
bc3130d196
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add XML parser for simulation setting
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2020-01-18 15:40:20 -07:00 |
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tangxifan
|
0de9908d52
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add accessors to simulation setting data structure
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2020-01-18 12:51:25 -07:00 |
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tangxifan
|
7a46c85cb0
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reorganize and clean-up sample architecture
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2020-01-18 10:50:15 -07:00 |
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tangxifan
|
ab1b1b7e02
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add XML writer for technology library
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2020-01-17 20:02:56 -07:00 |
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tangxifan
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8f2936af54
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finish XML parser for technology library
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2020-01-17 17:43:55 -07:00 |
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tangxifan
|
d58186507c
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add XML parsing for device model library settings
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2020-01-17 17:15:58 -07:00 |
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tangxifan
|
88a96673e3
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rename some methods in technology library and start building associated XML parser
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2020-01-17 16:44:57 -07:00 |
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tangxifan
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771f2d9c37
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developing data structure TechnologyLibrary to store technology-related information
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2020-01-17 10:17:15 -07:00 |
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tangxifan
|
aa070b2a41
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further clean-up sample arch.xml
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2020-01-17 09:38:35 -07:00 |
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tangxifan
|
910c69d7e5
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clean up and reorganize XML about technology library
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2020-01-17 09:24:58 -07:00 |
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tangxifan
|
5c69f57559
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sample_arch:move cmos/rram variation to technology library XML nodes
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2020-01-16 20:58:45 -07:00 |
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tangxifan
|
95edd3c091
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clean up the sample arch
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2020-01-16 20:52:47 -07:00 |
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tangxifan
|
9ba42cd540
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add XML writer for circuit ports
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2020-01-16 16:05:11 -07:00 |
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tangxifan
|
0304d723c0
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add XML writer for design technology of a circuit model
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2020-01-16 14:45:41 -07:00 |
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tangxifan
|
e282f813bc
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rename circuit settings to openfpga arch and update sample architecture
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2020-01-15 20:28:04 -07:00 |
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tangxifan
|
602d0bde4c
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add XML parsing for wire parasitics in circuit model
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2020-01-15 19:54:57 -07:00 |
|
tangxifan
|
a9b122d584
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add XML parsing for buffer models in circuit library
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2020-01-15 15:27:49 -07:00 |
|
tangxifan
|
5937ffc809
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add XML parsing for buffer/pass-gate-logic -related properties
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2020-01-14 15:44:24 -07:00 |
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tangxifan
|
56113e1aab
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adding XML parsing for design tech of circuit model
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2020-01-14 14:10:00 -07:00 |
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tangxifan
|
82d83ddceb
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reorganized the read XML openfpga arch
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2020-01-14 08:33:48 -07:00 |
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tangxifan
|
e2f641fdb3
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add example architecture for openfpga and developing XML parser
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2020-01-12 22:39:38 -07:00 |