Commit Graph

24 Commits

Author SHA1 Message Date
tangxifan 434c0d9683 hot fix on tutorial 2019-07-18 13:39:47 -06:00
AurelienUoU a47711203c Tuto update draft 5 2019-07-10 14:59:03 -06:00
AurelienUoU 905293820f Draft2 2019-07-10 10:37:05 -06:00
AurelienUoU 8366f9e7b7 Update tutorial 2019-07-08 16:18:08 -06:00
Ganesh Gore 443a73954f Removed all local files
+ Removed local configurations and scripts from previous commit
2019-07-03 14:26:06 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
tangxifan ec3b4c86c4 update file organization and be ready for SB/CB class 2019-05-21 12:15:38 -06:00
AurelienUoU fbebb45bf2 Path correction in config file 2019-05-20 11:13:30 -06:00
AurelienUoU df8bb0db1a Add MCNC Benchmarks netlists generation to travis regression test 2019-05-17 15:22:04 -06:00
Baudouin Chauviere 79930982cf Changed for the naming 2018-12-08 16:19:38 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script 2018-11-30 21:14:43 -07:00
Baudouin Chauviere d55ecd154b Add the PTM to the benchmark flow 2018-11-21 11:32:34 -07:00
Baudouin Chauviere 8ce0a84bc1 Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00
Baudouin Chauviere 03e902023a Perl script integrated to flow. rm shell one 2018-11-20 13:32:11 -07:00
Baudouin Chauviere 15d69e2bb1 Generation script finished TODO: integration in flow 2018-11-20 13:24:31 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
Baudouin Chauviere e5c6471fc2 Update of the Readme and added an example
ReadMe is now cleaner
2018-10-03 17:10:29 -06:00
Xifan Tang 1cf066d3ad Fixing minor bugs 2018-09-06 14:25:23 -06:00
Xifan Tang c009a37580 fix minor bugs 2018-09-04 17:56:37 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
Xifan Tang 90669d19c5 Update FPGA-SPICE and flow configurations 2018-08-09 11:27:16 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00