Commit Graph

1875 Commits

Author SHA1 Message Date
tangxifan 3b3c39454b update print_route() in VPR to show correct track_id when tileable routing is used 2020-03-25 17:55:28 -06:00
Xifan Tang b4221e94bb add documentation on the tileable routing and thru channel support 2020-03-25 16:52:42 -06:00
Xifan Tang cb6afea07c update documentation on a new option in FPGA-SDC to constrain zero-delay paths 2020-03-25 16:00:25 -06:00
tangxifan 329b0a9cf1 add options to enable SDC constraints on zero-delay paths 2020-03-25 15:55:30 -06:00
Xifan Tang 3a74fb7a04 update documentation for the new options 2020-03-25 15:23:21 -06:00
tangxifan 4a0128f240 minor fix on the SDC format 2020-03-25 14:46:31 -06:00
tangxifan 62b6de8437 update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA 2020-03-25 14:44:42 -06:00
tangxifan c2e5d6b8e2 add options to dsiable SDC for non-clock global ports 2020-03-25 14:38:13 -06:00
tangxifan 787dc8ce83 added ASCII OpenFPGA logo in shell interface 2020-03-25 11:16:04 -06:00
tangxifan b6bdf78d95 bug fixed for heterogeneous block instances in top module 2020-03-24 17:39:26 -06:00
tangxifan 610c71671f experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
2020-03-24 16:47:45 -06:00
tangxifan 8a996ceae5 bug fixed in tileable routing when heterogeneous blocks are considered;
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
tangxifan 08b46af7be add micro architecture for heterogeneous FPGA with single-mode DPRAM 2020-03-24 12:20:51 -06:00
Xifan Tang 7e3a8e5794 typo fixed in fpga-bitstream documentation 2020-03-22 16:27:12 -06:00
Xifan Tang 75dfe6a045 update documentation for write_gsb_to_xml functionality 2020-03-22 16:21:35 -06:00
tangxifan 9e4e12aae9 fixed echo message in the compression rate of gsb uniquifying 2020-03-22 16:13:04 -06:00
tangxifan ff474d87de fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs 2020-03-22 16:11:00 -06:00
tangxifan fdf6a6bd3e use chan_node_in_edges from rr_gsb in XML writer 2020-03-22 15:48:11 -06:00
tangxifan 3958ac2494 fix bugs in flow manager on default compress routing problems 2020-03-22 15:26:15 -06:00
tangxifan fc6abc13fd add physical tile utils to identify pins that have Fc=0 2020-03-21 21:02:47 -06:00
tangxifan 7b9384f3b2 add write_gsb command to shell interface 2020-03-21 19:40:26 -06:00
tangxifan 637be076dc adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working 2020-03-21 18:49:20 -06:00
tangxifan 9a518e8bb6 bug fixed for tileable rr_graph builder for more 4x4 fabrics 2020-03-21 18:07:00 -06:00
tangxifan 63c4669dbb fixed bug in the fast look-up for tileable rr_graph 2020-03-21 17:36:08 -06:00
tangxifan c0e8d98c6f bug fixed in tile direct builder 2020-03-21 12:43:56 -06:00
tangxifan 8f35f191eb use the formalized function in FPGA-SDC to identify direct connection 2020-03-21 11:42:00 -06:00
tangxifan 28123b8052 remove the direct connected IPIN/OPIN from RR GSB builder 2020-03-21 11:38:39 -06:00
tangxifan 2ff2d65e58 start debugging tileable routing using larger array size. Bug spotted in finding chan nodes 2020-03-20 22:12:23 -06:00
tangxifan 682b667a3c minor bug fix for direct connection in FPGA-SDC 2020-03-20 21:44:01 -06:00
tangxifan 05ec86430a temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT! 2020-03-20 17:56:03 -06:00
tangxifan 3c37b33f17 critical bug fixed in edge sorting for rr_gsb 2020-03-20 17:45:50 -06:00
tangxifan 060c1a41d9 critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted 2020-03-20 17:23:19 -06:00
tangxifan 2c0c5a061b spot a bug in assigning rr_switch in tileable routing 2020-03-20 16:53:43 -06:00
tangxifan 708fda9606 fixed a bug in using tileable routing when directlist is enabled 2020-03-20 16:38:58 -06:00
tangxifan c5049a1ec8 keep debugging tile direct connections 2020-03-20 15:10:00 -06:00
tangxifan a46fc9f028 add debugging information for tile direct builder 2020-03-20 14:59:46 -06:00
tangxifan 9837be618d start debugging tile direct with micro architecture 2020-03-20 14:52:52 -06:00
tangxifan a0b150f12e adding micro architecture using adder chain 2020-03-20 14:18:59 -06:00
tangxifan 8d57808d07 add missing files for micro benchmarks 2020-03-20 11:08:55 -06:00
tangxifan 3647548526 clean up on the shell echo commands 2020-03-20 11:07:45 -06:00
tangxifan 808853db0b critical bug fixed for find proper pb_route traceback 2020-03-13 12:26:37 -06:00
tangxifan 81e5af464e improve lb_route to avoid routing combinational loops 2020-03-12 23:58:56 -06:00
tangxifan 773e6da308 Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree 2020-03-12 22:53:17 -06:00
tangxifan f90dc5c296 remove redundant XML codes 2020-03-12 20:44:07 -06:00
tangxifan 29450f3472 debugging multi-source lb router 2020-03-12 20:42:41 -06:00
tangxifan 8921905bec annotate multiple-source and multiple-sink nets from pb to lb router 2020-03-12 19:21:13 -06:00
tangxifan f0b22aaa11 Make lb router support multiple sources to be routed 2020-03-12 13:44:14 -06:00
tangxifan c40675ca9d minor code formatting 2020-03-12 11:55:25 -06:00
tangxifan f1e8e78410 minor code formatting 2020-03-12 11:47:42 -06:00
tangxifan 689c50dff1 label the routing status for each sink in lb_router 2020-03-12 11:36:31 -06:00