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OpenFPGA
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3692 Commits

Author SHA1 Message Date
ganeshgore 3c9c089e64
Merge pull request #307 from lnis-uofu/io_map_file 
Output I/O mapping information to XML file
 2021-04-27 17:19:07 -06:00
tangxifan 8728fd9561 [Tool] Typo fix to resolve clang errors 2021-04-27 15:06:07 -06:00
tangxifan 1bae59dc6a [Doc] Update documentation for the write_io_mapping command 2021-04-27 14:54:57 -06:00
tangxifan 6cb4d7d720 [Test] Add the new test to regressiont test 2021-04-27 14:41:38 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00
tangxifan f9fd444b86 [Script] Add an write I/O mapping example script for openfpga shell 2021-04-27 14:40:26 -06:00
tangxifan c5d36757c6 [Tool] Fix typo in io mapping writing 2021-04-27 14:39:57 -06:00
tangxifan 43c1e052ef [Tool] Add a writer to output I/O mapping information to XML files 2021-04-27 14:30:16 -06:00
tangxifan 33c12c8f0e
Update CMakeLists.txt 2021-04-26 20:51:54 -06:00
tangxifan 5296e376f1
Merge pull request #305 from lnis-uofu/micro_benchmarks 
Test addition for FPGA architecture with multi-width DSP blocks
 2021-04-26 17:43:56 -06:00
tangxifan 1d5e926d9e [Test] Deploy new test to CI 2021-04-26 16:29:54 -06:00
tangxifan 6291871faf [Test] Added a test for the example architecture with 2x2 DSP blocks 2021-04-26 16:28:43 -06:00
tangxifan 8c007c7c49 [Arch] Add a new example architecture where a DSP block occupies a 2x2 grid 2021-04-26 16:28:10 -06:00
tangxifan 64704f52eb
Merge pull request #304 from lnis-uofu/tileable_rr_graph 
Tileable rr graph
 2021-04-26 14:11:16 -06:00
tangxifan 3b50d00b30
Merge branch 'master' into tileable_rr_graph 2021-04-26 12:12:57 -06:00
tangxifan 9a8d109d85
Merge pull request #303 from lnis-uofu/tangxifan-patch-1 
Update PULL_REQUEST_TEMPLATE.md
 2021-04-26 12:06:23 -06:00
tangxifan 05f08c2f25
Update PULL_REQUEST_TEMPLATE.md 2021-04-26 12:05:37 -06:00
tangxifan 7d4c5e3cd1 [Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block 2021-04-26 12:00:57 -06:00
tangxifan 6e87b8875b [Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block 2021-04-26 11:59:25 -06:00
tangxifan cbd7105083 [Tool] Add illustrative comments to tileable rr_graph generator 2021-04-26 11:57:17 -06:00
tangxifan 880624e699 [Tool] Update comments in tileable rr_graph generator to be easier to be understood 2021-04-26 11:48:02 -06:00
ganeshgore d7426808ba
Merge pull request #299 from hitblunders/master 
Updated compile.rst
 2021-04-26 00:26:07 -06:00
ganeshgore ab34ebecef
Merge pull request #301 from lnis-uofu/tangxifan-patch-1 
Update bug_report.md
 2021-04-26 00:25:26 -06:00
ganeshgore cb38455a52
Merge pull request #302 from lnis-uofu/tangxifan-patch-2 
Update pull_request_template.md
 2021-04-26 00:25:14 -06:00
tangxifan deb9f4a9f7
Update pull_request_template.md 2021-04-25 22:11:34 -06:00
tangxifan a8b2966709
Update bug_report.md 2021-04-25 22:08:17 -06:00
tangxifan 83167b6b61
Update bug_report.md 2021-04-25 22:06:13 -06:00
tangxifan 4b8dab0913
Update bug_report.md 2021-04-25 20:51:29 -06:00
tangxifan 386dbf8c1a
Update pull_request_template.md 2021-04-25 18:30:48 -06:00
tangxifan 94c575fa74
Update bug_report.md 2021-04-25 18:12:12 -06:00
tangxifan 1baee10e61
Merge pull request #298 from lnis-uofu/micro_benchmarks 
Micro benchmarks addition and testing for FPGAs with DSP blocks
 2021-04-24 17:55:38 -06:00
tangxifan 62dc5a3856 [Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes 2021-04-24 16:02:24 -06:00
tangxifan b7da22501c [Test] Deply new test to regression test 2021-04-24 15:55:05 -06:00
tangxifan 5adffad602 [Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!! 2021-04-24 15:49:53 -06:00
tangxifan 80f98328df [Test] Update test settings for architecture with fracturable DSP blocks 2021-04-24 15:16:50 -06:00
tangxifan 8b8096f3a8 [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan 272d1fffb7 [HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks 2021-04-24 13:30:46 -06:00
tangxifan ddcdb35b28 [Arch] Bug fix in single-mode 8-bit DSP architectures 2021-04-24 13:30:03 -06:00
tangxifan 1c6b9a23d7 [Test] Add new test for multi-mode 16-bit DSP blocks 2021-04-24 13:29:29 -06:00
tangxifan 0709e5bb81 [Tool] Fixed a bug in the routing trace finder for direct connections inside repacker 2021-04-24 13:27:44 -06:00
Parnabrita Mondal cc92c27fde
Update compile.rst 2021-04-24 14:01:52 +05:30
tangxifan c44688739d [HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks 2021-04-23 22:12:26 -06:00
tangxifan 09cc7f0007 [Script] Enable constant net routing for heterogeneous FPGAs 2021-04-23 20:44:36 -06:00
tangxifan 189c94ff19 [Test] Deploy new mac benchmarks to tests 2021-04-23 20:44:14 -06:00
tangxifan 200b6d39a6 [Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit 2021-04-23 20:36:28 -06:00
tangxifan 671394ec2c [Benchmark] Add microbenchmarks for mac with different sizes for DSP testing 2021-04-23 20:33:43 -06:00
tangxifan 5ce28158bd
Merge pull request #297 from lnis-uofu/iwls2005 
Enable constant net routing for VTR benchmarks
 2021-04-23 16:52:35 -06:00