- update comments to say so.
- update docs to clarify that the "arm9tdmi" command prefix
is a misnomer.
- bugfix some messages that wrongly assume only ARM9TDMI
based processors use this code.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2719 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Cleanup some the downloaded ARM target algorithm code:
- Provide more complete disassembly of the DCC bulk write code
- Make code blocks "static const", in case GCC doesn't
- Fix some tabbing/layout issues
- Make some arm7_9_common.h flags be "bool" not "int"; and compact
the layout a bit (group most bools together)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2698 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch adds target algorithm support for those flash devices that do not support DQ5 polling. So far they could only be programmed with host algorithm, but this was way too slow.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2682 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Infinite loop bugfix when running tap configure a second time
git-svn-id: svn://svn.berlios.de/openocd/trunk@2681 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Provide an "armv7a disassemble" command. Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
lean up some loose ends with the ARM disassembler
- Add a header comment describing its current state and uses
and referencing the now-generally-available V7 arch spec
- Support some mode switch instructions:
* Thumb to Jazelle (BXJ)
* Thumb to ThumbEE (ENTERX)
* ThumbEE to Thumb (LEAVEX)
- Improve that recent warning fix (and associated whitespace goof)
- Declare the rest of the internal code and data "static". A
compiler may use this, and it helps clarify the scope of these
routines (e.g. what changes to them could affect).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.
Have davinci_nand do so. This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.
NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2663 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Via code review by Steve Grubb <sgrubb@redhat.com>
Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Via code review by Steve Grubb <sgrubb@redhat.com>
Also minor fixes for the message from "fill": the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written
git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
on the command line ... matching comment in add_default_dirs().
Without this it's impossible to use a private config file which
happens to have the same name as an installed one. Say, because
you're bugfixing a private copy...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
that were added after ARMv5TE was defined:
- ARMv5J "BXJ" (for Java/Jazelle)
- ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)
Compile-tested. This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).
ARMv6 instructions known to be mis-handled by this disassembler
include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2
git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
"next iteration" step with the rest of the loop overhead.
Cleanup: remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bugfixes:
* internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
+ except new Tempest parts where it's 16 MHz (and calibrated!)
+ or some old Sandstorm ones, where 15 MHz was valid
* crystal config:
+ read and use the crystal config, don't assume 6 MHz
+ know when that field is 4 bits vs 5
* an RCC2 register may be overriding the original RCC
+ more clock source options
+ bigger dividers
+ fractional dividers on Tempest (NYET handled)
* there's a 30 KHz osc on newer chips (for deep sleep)
* there's a 32768 Hz osc on newer chips (for hibernation)
- Cosmetic
* say "rev A0" not "vA.0", to match vendor docs
* don't always report master clock as an "estimate":
+ give the error bound if it's approximate, like "±30%"
+ else don't say anything
* fix whitespace and caps in some messages
* these are not AT91SAM chips!!
Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.
That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor. What's less clear is which chips are "old" like that.
Lightly tested, on a DustDevil part.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Unify the handling of the req_srst parameter, and rip out a
large NOP branch and its associated FIXME. (There didn't seem
to be anything that needs fixing; but that was unclear since
the constraints were scattered all over the place not unified.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2623 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Unify the handling of the req_tlr_or_trst parameter. Basically,
JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe
option in this system configuration.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2622 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Track whether TRST and/or SRST actually change:
* If they're not changing, don't ask the JTAG adapter to do anything!
(JTAG TCK/TMS ops might still be used to enter TAP_RESET though.)
* Don't change their recorded values until after the adapter says it
did so ... so fault paths can't leave corrupt state.
* Detect and report jtag_execute_queue() failure mode
* Only emit messages saying what really changed; this includes adding
an omitted "deasserted TRST" message.
* Only apply delays after deasserting SRST/TRST if we *DID* deassert!
- Messages say "TLR" not "RESET", to be less confusing; there are many
kinds of reset. (Though "TLR" isn't quite ideal either, since it's
the name of the TAP state being entered by TMS+TCK or TRST; it's at
least non-ambiguous in context.)
So the main effect is to do only the work this routine was told to do;
and to have debug messaging make more sense.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2621 b42882b7-edfa-0310-969c-e2dbd0fdcd60
reset operations. Maybe they can't; or it's a "not yet" thing.
Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)
This code has mainly been developed and tested against R1606, it has
been built and tested against R2294 where it runs but step and resume
commands are broken due to regression (which should be fixed now).
This code is really written for OMAP3530. It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection. The OMAP3530 DAP exposes two memory access ports:
- Port #0 is connected to L3 interconnect (the main bus) with
passthrough to the L4 EMU bus ... so it will be used for most
memory accesses.
- Port #1 is connected to a dedicated debug bus (L4 EMU), with
access to L4 Wakeup, and holds the ROM table ... so it must
be used for most debug and control operations.
The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code. Having access to another Cortex-A8
implementation would help get that right.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from Øyvind and Dave.)
The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.
The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions. Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too. There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
The trunk is currently broken for interfaces without
the speed_div function (interface specific clock speed
value to kHz conversion). Example: parport.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2605 b42882b7-edfa-0310-969c-e2dbd0fdcd60
SVF file, making OpenOCD compatible with files generated by
Altera Quatrus II 9.0.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2600 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- warning now issued if high speed ftdi device found and openocd was built using an old driver
git-svn-id: svn://svn.berlios.de/openocd/trunk@2599 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler. LDREX and STREX are not
issued by GCC without inline assembly.
This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled. Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- spell "address" right
- list bp/wp params as optional
And make those source lines wrap at sane margins.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- AIRCR_SYSRESETREQ is generic; use it on any system where
SRST won't fly, not just on Stellaris-based ones.
- Reformat and improve comments about the Stellaris quirk; and
xref the only public docs (an email) about the issue.
It seems that *most* Stellaris chips have this problem. Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Simplify dumping of register lists by only printing cached values
if they are marked as valid. Most of the time, they are invalid;
so printing *any* value is just misleading.
Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html
1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H
since version 0.16
2. A speed value of 0 is used as a RTCK request indicator. This clashes with the
valid clock division value 0 that provide the highest fixed clock frequency.
3. The ft2232_speed_div function return the maximum selectable frequency (30MHz)
when RTCK is activated. It should return 0.
4. The ft2232_khz function return ERROR_OK when RTCK is requested even for
devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers
can detect this and try to fallback to a fixed frequency.
5. FT2232H/FT4232H have a backward compatibility function that divide the clock
by 5 to get the same frequency range as FT2232D. There is no code that disable
this functionality. I can not find anything about if this is enabled or disabled by default.
I think it is safest to actively disable it.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2591 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Change jtag_rclk behaviour so it can be called before the interface init function
git-svn-id: svn://svn.berlios.de/openocd/trunk@2590 b42882b7-edfa-0310-969c-e2dbd0fdcd60
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
display them as 32 bits unless that's their true size.
(Removes some confusion.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
OpenOCD was able to access only to chips attached to first EMIF
chipselect. This patch fixes chipselect management code and allows
OpenOCD to access to NAND devices attached to any EMIF CS line.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Add flash programming support for NXP LPC1700 cortex_m3 based family
git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- revert patch from rev1507 as it was causing reset issues with arm9 cores
git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.11 Data processing (shifted register)
The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes. There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M arch manual:
A5.3.1 Data processing (modified immediate)
A5.3.3 Data processing (plain binary immediate)
A5.3.4 Branches and miscellaneous control
and other (immediate) encodings referenced there. Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:
A5.3.12 Data processing (register)
A5.3.13 Miscellaneous operations
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, and divide
The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Dump SP on poll, and show whether it's MSP or PSP.
Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.
Shrink some lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Minor updates to the Thumb2 disassembly:
- Bugfixes:
* Distinguish branch from misc via "!=" not "=="
* MRS register shift is 8 bits (vs MSR being 16)
- Format tweaks:
* CPS needed tab (not space)
* add commma before some shifts
* add space after comma in LDM/STM
* use ".W" width spec on various instructions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus
git-svn-id: svn://svn.berlios.de/openocd/trunk@2551 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c. There should be no
change in functionality here. (From Magnus.)
Minor style cleanup: whitespace, line length, etc. Update spec
references to use docs which are currently available. (From Dave.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.5 Load/store multiple
The preferred PUSH/POP syntax is shown when appropriate.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, divide
The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More Thumb2 32-bit opcode support:
A5.3.10 Store single data item
Byte, word, halfword. Offset, pre-index, post-index. And
a "make like you're unprivileged" option when using small
immediate offsets.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8"
instead of the architected NOP which is new in Thumb2.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make disassembly of the Thumb load-literal instruction show the
address of the literal being loaded (so users can avoid doing
that math themselves). Add and use an Align(PC,4) utility.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.3 Data processing (plain binary immediate)
These use mostly twelve bit literals, but there are also bitfield
and saturated add primitives.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.1 Data processing (modified immediate)
My small sample shows GCC likes to use many of these instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle a bunch of 32-bit instructions:
A5.3.4 Branches and miscellaneous control
Note that this shifts some responsabililty out of helper functions,
making the code and layout simpler for 32-bit decoders: they only
need to know how to format the instruction and its parameters.
Also, technical note: with this patch, Thumb1 decoders could now
call the Thumb2 decoder if they wanted to get nicer treatment of
the exiting 32-bit B/BLX instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Change layout of Thumb disassembly to work better with Thumb2:
- Move opcode to the left, allowing space for four hex bytes:
* after address, two spaces not one tab (taking 6 spaces)
* after 2-byte opcode, four spaces before tab
- Also, after opcode mnemonic use a tab not a space, to make
operands line up
Sample output (after some patches decoding a few 32-bit instructions):
0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000
0x00003e5e 0x601a STR r2, [r3, #0x0]
0x00003e60 0x2800 CMP r0, #0x00
0x00003e62 0xd1f3 BNE 0x00003e4c
0x00003e64 0xf008fa38 BL 0x0000c2d8
The affected lines of code now wrap at sane margins too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Initial support for disassembling Thumb2 code. This works only for
Cortex-M3 cores so far. Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.
- Update the 16-bit Thumb decoder:
* Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
by ARMv6. (It already seems to treat CPY as MOV.)
* Understand CB, CBNZ, WFI, IT, and other opcodes added by
in Thumb2.
- A new Thumb2 instruction decode routine is provided.
* This has a different signature: pass the target, not the
instruction, so it can fetch a second halfword when needed.
The instruction size is likewise returned to the caller.
* 32-bit instructions are recognized but not yet decoded.
- Start using the current "UAL" syntax in some cases. "SWI" is
renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".
- Define a new "cortex_m3 disassemble addr count" command to give
access to this disassembly.
Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch correctly identifies a running target.
Patch made a tad more palatable by David Brownell <david-b@pacbell.net>
git-svn-id: svn://svn.berlios.de/openocd/trunk@2510 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Updates to private TAP state tables in amtjtagaccel interface driver.
The first change is the neccesary one to correct a long-standing bug that
caused the IDCODE to be shifted by one bit too many. This was caused by
an incorrect path from state RESET to state DRSHIFT.
The value of those 2 bytes were 0x8a and 0x04. This means that the
bitstream to do this transition is 0b 00100 01010 (send LSB first). This
will bring you from the reset state to the shift state; however, you
enter the shift-state twice, which explains why the ID-CODE that will be
read next will be shifted 1 bit. The fix changes these to 0x05 and 0x00.
This will send the bitstream 0b 00101 (send LSB first). This will bring
the TAP controller from the RESET state to the DRSHIFT state directly,
without entering the DRSHIFT state twice.
After checking the whole table, two other transitions were found that
could be optimized (5 bits in stead of 10 bits).
Summary off all changes:
From To Old values Old Bitstream New values New Bitstream Remarks
---- ------- ---------- ------------- ---------- ------------- -------
RESET DRSHIFT 0x8a 0x04 0b00100 01010 0x05 0x00 0b00101 1,2
IDLE DRSHIFT 0x85 0x08 0b01000 00101 0x04 0x00 0b00100 2
IDLE IRSHIFT 0x8b 0x08 0b01000 01011 0x06 0x00 0b00110 2
[1] Fixes the IDCODE bug
[2] Optimization
git-svn-id: svn://svn.berlios.de/openocd/trunk@2472 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix intermittent J-Link interface startup failures:
- Use usb_reset to ensure selected dongle is in known good state.
- Assert emulator reset durning status check to prevent supurious failures.
- Eliminate status check loop; not needed due to other fixes.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2471 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Restore some whitespace that got clobbered by over-aggressive
whitepace eradication patches a while back.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2446 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch adds support for the Luminary Micro LM3S9B90 target and
LM3S9B92 Evaluation Kit. These kits include a new ft2232 adapter, the
Luminary In-Circuit Debug Interface (ICDI) Board, so this is added as a
new ft2232 layout called "luminary_icdi".
git-svn-id: svn://svn.berlios.de/openocd/trunk@2429 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Add "jtag names" command, mirroring "target names" but returning
TAP names instead of target names. This starts letting TAPs be
manipulated in scripts ... much like what works now for targets.
It's a bit limited just yet, since "jtag cget $TAPNAME" doesn't
expose all TAP attributes. "$TARGETNAME cget" is more functional.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2428 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move repository URL output associate it with the version; they relate.
- 'openocd --version' output now appears much more terse, as expected.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2421 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Remove some bogus warnings during server startup for ARM926ejs
targets that were already halted for debug ... e.g. started up
a freshly built instance.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2417 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Warn when people (or scripts) use numeric identifiers for TAPs,
instead of dotted.name values. We want this usage to go away,
so that for example adding more TAPs doesn't cause config scripts
to break because some sequence number changed.
It's been deprecated since late 2008, but putting a warning on
this should help us remove it (say, in June 2010) by helping to
phase out old (ab)usage in config scripts.
Other than in various config files, the only code expecting such
a number was the almost unused str9xpec driver. This code was
changed to use the TAP it was passed, instead of making its own
dubious lookup and ignoring that TAP.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2415 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Adds new source files to encapsulate static/dynamic module handling.
- Further work should implement the jtag_interface_modules_load routine,
to populate the jtag_interfaces list from shared libraries in a path.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2413 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- issue is gdb stdin buffer gets full before we redirect openocd output
git-svn-id: svn://svn.berlios.de/openocd/trunk@2350 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This is minimal patch to support FA526 ARMv4 compatible core.
Since it is very similar to ARM920T I tried to reuse as much
code as possible.
CPU and board configs will follow soon.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2292 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Clean up the PLD files:
- Get rid of some extraneous whitespace
- Make various functions static
- Wrap overlong lines
git-svn-id: svn://svn.berlios.de/openocd/trunk@2272 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Let jtag_call_event_callbacks() behave when the callback removes itself.
Oddly, this crashed on x86_32 but not x86_64.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2264 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix parsing bugs for "$target_name mww addr data [count]" ... it was
always requiring the count, instead of just defaulting it to one.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2263 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use macro to eliminate duplicate body definitions.
- Rename okay as is_okay; add parenthesis to help "clarify" logic.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2253 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix a bug preventing ICEpick "enable that TAP" code from working:
the "runtest" command wrongly finished with a JTAG reset, discarding
the work the TAP enable handler just finished! Instead, JTAG should
stay in RUN/IDLE state.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2252 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Extend the internal JTAG event handlers to cover enable/disable,
and use those events to make sure that targets get "examined" if
they were disabled when the scan chain was first set up:
- Remove "enum jtag_tap_event", merge with "enum jtag_event",
so C code can now listen for TAP enable/disable events.
- Report those events so they can trigger callbacks.
- During startup, make target_examine() register a handler to
catch ENABLE events for any then-disabled targets.
This fixes bugs like "can't halt target after enabling its TAP".
One class of unresolved bugs: if the target has an ETM hooked
up to an ETB, nothing activates the ETB. But starting up the
ETM without access to the ETB registers fails...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2251 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Tighten error handling on TAP enable/disable paths a bit:
- Don't enable/disable unless it's necessary. Those event
handlers could have nasty side effects...
- Don't *succeed* enables/disables if there was no code which
could have implemented that action. This prevents bugs like
wrongly acting as if the scan chain changed.
- Minor whitespace cleanup in enable/disable command code.
The big problem is still the lack of code to verify scan chains
were actually updated as requested; this adds a comment on that.
I suspect the best we can do near term will be to verify IDCODE.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2250 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix bug in a warning. It warned about "huge IRlength" for an
older JRC with a two bit instruction register ... wrong!
git-svn-id: svn://svn.berlios.de/openocd/trunk@2249 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix some polling issues:
- Don't background-poll disabled TAPs ... this was just a bug
waiting to happen. (And then it happened!)
- Don't fail command line polls of disabled taps; that's not any
kind of error, it's just that you can't do much. But do show
that tap-disabled status.
- Spell "continuous" correctly in the variable name. ;)
Not resolved by this patch: the need for an interlock whereby
other code (like the JTAG layer) can block all other access to
the JTAG layer, e.g. while enabling or disabling TAPs. And
that interlock needs to be timer-safe...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2247 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Doc update: say "jtag newtap ... -disable" records the
state after exiting the RESET state, matching the only
implementation we're working with so far (TI ICEpick-C).
Matching code updates. Now we can be sure that the
"enabled" flag value is correct after JTAG resets.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2246 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix a memory leak in jtag_tap_free(): unregister the event
callback too.
Also fix the associated conceptual bug in unregistering JTAG
event callbacks: since the same callback procedure is used
many times with different callback data (a TAP handle), that
data must be considered when unregistering any callback.
This could fix some crashes after TAP registration errors,
by making sure the reset event handler doesn't scribble over
memory that's now used by something else.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2245 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Minor jtag cleanup:
- remove hidden assumption about JTAG event numbering
- move function declarations to a header
- some end'o'line whitespace
- use "calloc" not "malloc + memset"
git-svn-id: svn://svn.berlios.de/openocd/trunk@2244 b42882b7-edfa-0310-969c-e2dbd0fdcd60
OpenOCD doesn't actually *need* to be keeping all TCP ports
active ... creating security issues in some network configs.
Instead, let config file specify e.g. "tcl_port 0" (or gdb_port,
telnet_port) to disable that particular remote access method.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2240 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Make fast_load_image use the helper coverage the standard load_image.
- Improve whitespace in the moved lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2239 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Simplify argument parsing logic using switch statement.
- Use parse_u32 to ensure all values parse properly.
- Return syntax error when mode argument fails to parse.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2236 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return syntax error if remove called without one argument.
- Use parse_u32 to ensure address and length arguments parse properly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2235 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Change: All local variable types are now unsigned.
- Use parse_u32 to ensure address and value parse properly.
- Use parse_uint to ensure count parses properly.
- Move variables to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2231 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use parse_u32 and parse_uint for address and count, respectively.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2230 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Make argument check use parse_uint to ensure value parses properly.
- Move variable declarations to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2228 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use unsigned type for delay variable.
- Use parse_uint to ensure delay argument parses properly.
- Bug fix: Return syntax error if more than one argument is given.
- Bug fix: Return syntax error when argument fails to parse.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2227 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Currently the "debug_level 3" command tracing ignores commands
that could return values to TCL scripts (by plugging in to a
slightly lower level of the interpreter stack).
Fix that by abstracting the tracing command and starting to
make some of those previously-untraced commands use this new
mechanism.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2224 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Partial fix to the "long IR length" problems.
- Current code could handle up to 32 bit IR lengths with
full functionality, if it didn't just reject may of them
out of hand. So only reject clear errors, where the IR
mask (or capture instruction) needs more than IrLen bits.
- Longer IR lengths can only be handled in BYPASS mode
for now. Example: TI's DSPs use 38-bit IR lengths.
So we can't issue their IDCODE instructions...
A more complete fix would be able to issue longer instructions;
or minimally, would fail cleanly for the non-BYPASS case.
Note that this *could* make some currently broken scripts fail,
since the previous code accepted garbage values so long as
they didn't use more than 16 bits.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2222 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move the mips32_..._read_mem calls to top-level of read_mem function.
- Change: Only perform mips_m4k_read_mem conversion when retval == ERROR_OK.
- Prevents pointless conversions of bogus read values after failures.
- Eliminate retval variable from mips_m4k_write_mem; return directly.
- Move declaration of retval variable to point of first use.
- Remove the now redundant switch statements testing size:
- argument sanitizing already covers these cases.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2220 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch helps fix MIPS big endian (elf32-tradbigmips) targets.
If "-endian big" is not set in target create, the endianess defaults to
little. mw and md commands will still work, but binary file loads will
have the incorrect word order loaded into memory.
The EJTAG processor access data register (PrAcc) is little endian
regardless of the CPU endianness; it is always loaded LSB first. This
is confirmed by the fact that mips_ejtag_drscan_32() uses buf_set_u32()
to load the scan field; buf_set_u32() is a little-endian formatter. For
big endian targets, data buffers have to be modified so the LSB of each
u32 or u16 is at the lower (first) memory location. If the drscan
out_value word order is set using buf_set_u32() then it makes sense to
also fixup the in_value with buf_get_u32(); a symmetry argument. This
has no affect on little endian hosts.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2219 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use the default KHz speed setting, in case interface is not initialized.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2218 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: Always clear high bit of USB bulk out endpoint.
- Use parse_ulong helpers to ensure numeric strings are parsed properly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2217 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use parse_uint helper to ensure argument is parsed properly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2216 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: Return a syntax error when less than two arguments are given.
- Bug fix: Use parse_u16 helper to ensure vales are parsed properly.
- Simplify loop termination logic by ensuring argc is always even.
- Move loop induction variable declaration to where it is used.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2215 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use parse_u32 helper to ensure scan values are parsed properly.
- Clear the fields buffer to ensure partial cleanup occur correctly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2214 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Show the port number to the user when asking for it or setting it.
- Print an error if the parport_port has already been set.
- Use parse_u16 helper to ensure the parport_port string parses correctly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2211 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Show the port number to the user when asking for it or setting it.
- Print an error if the amt_jtagaccel_port has already been set.
- Use parse_u16 helper to ensure amt_jtagaccel_port string parses correctly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2210 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Show the port number to the user when asking for it or setting it.
- Print an error if the parport_port has already been set.
- Use parse_u16 helper to ensure the parport_port string parses correctly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2209 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: Return a syntax error if more than one argument is given.
- Bug fix: Use new parse_uint helper ensure debug_level parses correctly.
- Change: Display the debug_level after it has been set.
- Simplify bounds checking of debug_level.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2208 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use new parse_ulong to ensure duration parses as a valid number.
- Rework logic to improve readability and seliminate uperfluous braces.
- Change whitespace to improve style.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2207 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Used to improve command argument parsing of unsigned integers values.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2206 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Minor bugfix: command_print_sameline() is what the
headers declare; make the code match.
Minor improvement: make the printf format params always be const.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2205 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Original patch submitted by David Claffey [dnclaffey@gmail.com].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2202 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return a syntax error if the wrong number of arguments are given.
- Add handle_bp_command_list() and handle_bp_command_set().
- Use temporary addr variable to eliminate redundant strtoul() calls.
- Place variable declarations at their point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2196 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add target_timer_callback_periodic_restart and target_call_timer_callback.
- Clean up and simplify logic that determines whether to call each callback.
- Move variable declarations to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2195 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add a doxygen block to simplify logic.
- Move declarations to point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2194 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Return syntax error unless exactly one argument is passed.
- Move variable declaration to point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2193 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Return syntax error if more than one argument is given.
- Move variables to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2192 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Eliminate redundant calls to target_resume with addr temp variable.
- Place variables at location of first use.
- Fix minor whitespace issues.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2191 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return syntax error when more than one argument is given.
- Eliminate redundant calls to step callback with addr temp variable.
- Place variables at location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2190 b42882b7-edfa-0310-969c-e2dbd0fdcd60
other server configuration. Explain what it's about;
reference the related "$target_name curstate" method.
Update "poll" output to report whether background polling
is enabled or not.
Also fix a small typo; PC's have "complementary" tools.
Some have also "complimentary" ones; but not all.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2178 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Remove once-used XXX_FTD2XX symbols; replace with XXX_DRIVER symbols.
- Enabled when either libftdi or FTD2xx driver should be built.
- Eliminates redundant DRIVERSFILE assignment in JTAG automake input.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2177 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Consolidate all individual driver variables into DRIVERFILES.
- Eliminates all empty 'else' conditional clauses.
- Move minidriver files to top of file.
- Use MINIDRIVER conditional to build only driver(s) that will be linked.
- Eliminate superfluous whitespace.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2176 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add new jtag_config_khz to increase encapsulation of jtag->khz call.
- Add new jtag_get_speed_readable to encapsulate of jtag->speed_div call.
- Make definition of jtag static in core.c, remove extern from tcl.c.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2171 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move jtag_event_callbacks struct to core.c; it's an implementation detail.
- Move jtag_*_event_callbacks next to the definition of the new function type.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Define the function signature used by the JTAG event callback mechanism.
- Provide Doxygen block for new type, including TODO for its return value.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2168 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move nvp_jtag_tap_event and jtag_tap_handle_event to tcl.c.
- Change both to be static; remove declaration of function from jtag.h.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2166 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add accessors for setting the jtag_verify_capture_ir flag.
- Use them in handle_verify_ircapture_cpmmand
- Change variable type to bool; make it static.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2164 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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