David Brownell <david-b@pacbell.net>:
More Thumb2 32-bit opcode support: A5.3.10 Store single data item Byte, word, halfword. Offset, pre-index, post-index. And a "make like you're unprivileged" option when using small immediate offsets. git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -2783,6 +2783,98 @@ do_adr:
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return ERROR_OK;
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}
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static int t2ev_store_single(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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unsigned op = (opcode >> 20) & 0xf;
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char *size = "";
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char *suffix = "";
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char *p1 = "";
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char *p2 = "]";
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unsigned immed;
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unsigned rn = (opcode >> 16) & 0x0f;
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unsigned rt = (opcode >> 12) & 0x0f;
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if (rn == 0xf)
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return ERROR_INVALID_ARGUMENTS;
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if (opcode & 0x0800)
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op |= 1;
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switch (op) {
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/* byte */
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case 0x8:
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case 0x9:
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size = "B";
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goto imm12;
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case 0x1:
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size = "B";
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goto imm8;
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case 0x0:
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size = "B";
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break;
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/* halfword */
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case 0xa:
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case 0xb:
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size = "H";
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goto imm12;
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case 0x3:
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size = "H";
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goto imm8;
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case 0x2:
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size = "H";
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break;
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/* word */
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case 0xc:
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case 0xd:
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goto imm12;
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case 0x5:
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goto imm8;
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case 0x4:
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break;
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/* error */
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default:
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return ERROR_INVALID_ARGUMENTS;
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}
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sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
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size, rt, rn, opcode & 0x0f,
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(opcode >> 4) & 0x03);
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imm12:
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immed = opcode & 0x0fff;
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sprintf(cp, "STR%s.W\tr%d, [r%d, #%u]\t; %#3.3x",
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size, rt, rn, immed, immed);
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return ERROR_OK;
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imm8:
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immed = opcode & 0x00ff;
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switch (opcode & 0x700) {
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case 0x600:
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suffix = "T";
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break;
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case 0x000:
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case 0x200:
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return ERROR_INVALID_ARGUMENTS;
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}
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/* two indexed modes will write back rn */
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if (opcode & 0x100) {
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if (opcode & 0x400) /* pre-indexed */
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p2 = "]!";
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else { /* post-indexed */
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p1 = "]";
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p2 = "";
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}
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}
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sprintf(cp, "STR%s%s\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
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size, suffix, rt, rn, p1,
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(opcode & 0x200) ? "" : "-",
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immed, p2, immed);
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return ERROR_OK;
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}
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/*
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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* always set. That means eventual arm_simulate_step() support for Thumb2
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@ -2842,6 +2934,10 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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else if ((opcode & 0x18008000) == 0x10008000)
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retval = t2ev_b_misc(opcode, address, instruction, cp);
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/* ARMv7-M: A5.3.10 Store single data item */
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else if ((opcode & 0x1f100000) == 0x18000000)
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retval = t2ev_store_single(opcode, address, instruction, cp);
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/* FIXME decode more 32-bit instructions */
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if (retval == ERROR_OK)
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