Reuse the flashless LPC4350 as base and amend it as necessary.
The LPC43x7 have 2x 512 KB of flash.
Change-Id: Ia7ffbc7101023479971984b839f171ed4be6b089
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3037
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Add support for the JTAG TAPID found on SK-FM4-U120-9B560-MEM V1.1.0 board.
Change-Id: Idbfe28927e0c549f0c89c29904d23971281927c9
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3039
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
It is found on the SK-FM4-U120-9B560-MEM V1.1.0 among others.
Change-Id: I4c708c9391e954cbbc8d0860a2a2dbd264aea865
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3008
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Its memory layout is different from MB9BFxxx.
Change-Id: I39c9f9cf582cd182971a9f83bb88c7a18da6cf15
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The XS1-XAU8A-10 has 8 xCORE cores and one ARM core.
This config represents the ARM Cortex-M3 core, which is apparently
Silicon Labs EFM32 Giant Gecko IP.
Change-Id: I998360f096c759d2e274d96c1ca2e0450ba61146
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2762
Tested-by: jenkins
Reviewed-by: Oleksij Rempel
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Flash driver "mini51.c" and "nuc1x.c" are same target MCU.
This patch integrates each driver and functions,
and makes into new "NuMicro" flash driver.
Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c
Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-on: http://openocd.zylin.com/2794
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
A target config and a simple flash driver for the ADuCM360 microcontroller.
The EEPROM of the chip may be erased and programmed.
Change-Id: Ic2bc2f91ec5b6f72e3976dbe18071f461fe503b8
Signed-off-by: Ivan Buliev <i.buliev@mikrosistemi.com>
Reviewed-on: http://openocd.zylin.com/2787
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Tested-by: jenkins
As found on the Parallella-I board SKU A101020.
Change-Id: Ie7e7a36325926d67fbe555b46a9be8a74fac8dba
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2729
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This covers only the Cortex-A5 for now, not the Cortex-M4.
Change-Id: I739ec52b14b83d6e9f124ed61f8941502e481402
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2766
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
code polishing to be consistent with other scripts
Change-Id: Ib52a92f48df9d2bdf543792b856e33aa04dbebe3
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Reviewed-on: http://openocd.zylin.com/2779
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Split TMS570 target into LS31/LS21 and LS20/LS10 targets.
Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI.
Tested attaching.
Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620
Signed-off-by: Alex Ray <a@machinaut.com>
Reviewed-on: http://openocd.zylin.com/2089
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use mmw to manipulate only selected bits of the word. msb and mwb verify the
memory location and may error on PLLRDY set as a result of PLLON written.
Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d
Reported-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2702
Tested-by: jenkins
This is a remake of http://openocd.zylin.com/1966
originally written by Angus Gratton <gus@projectgus.com>
ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU
in reset if TCK is low when srst (RESET_N) is deasserted.
Without this change any use of sysresetreq or srst locks the chip
in reset state until power is cycled.
A new function smap_reset_deassert is called as reset-deassert-post event handler.
It optionally prepares reset vector catch and SMAP reset is released then.
Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2604
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Assembled by trial-and-error for an S6E2CC.
Change-Id: I317c12d24c9075ce3de286455fa3ee45731c5c81
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2569
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Original submitted code had only been tested with em358, but testing with
actual em357 revealed errors that this patch corrects.
Change-Id: I70cf31210de8ed84e3755a56e76261ad200322bb
Signed-off-by: Ed Beroset <beroset@ieee.org>
Reviewed-on: http://openocd.zylin.com/2581
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Base config, verified against XMC4500, XMC4400 and XMC4100/XMC4200 manuals.
Change-Id: I10907bdf307bc6d11dc5454bf5391758de49dc30
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/2480
Tested-by: jenkins
Reviewed-by: Jeff Ciesielski <jeffciesielski@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
this is just to avoid open coding that in
icepick_d_tapenable. Cleanup only, no functional
changes.
Change-Id: Iabd20291b7bdd95957afa1c74f52171789201227
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2624
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
it also works on icepick_d.
Change-Id: I50c0c81286aae673c94ea77e47454ff48eab1668
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2623
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reusing what's already there to ease maintainability.
Change-Id: I2030581669c644e2d9d9f9968075ab6344445d04
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2622
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is only for the sake of completeness as
default coreid is zero. In any case, coreids 1-4 are
used for the different PRU cores inside the SoC.
Change-Id: I775f2f444b1a908ffaf7bdbc43bcc966f19668c4
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2621
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use more descriptive names for JRC and DAPs
so they more closely match documentation.
For example there's no Cortex A9 DAP, that's
the DebugSS DAP where Cortex A9 target sits. In
that same DAP we have have ETM, STM and both
dual-PRU subsystems.
Change-Id: I0e66ebb6299763f96606fae3e4c62e5785c804f2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2620
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Main DAP (where Cortex A9 sits) ID is actually
0x46b6902f. Fix it.
Change-Id: Ifa3335186bcf60d264d4ecea477bfe2f5ca10ead
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2619
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
this event handler will configure and lock PLLs
and configure DDR so platform is placed in usable
state.
Change-Id: Idd02f4c9789181d69578f8606ac3576ea1dd8a0b
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2616
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
sometimes, watchdog might be left running and
it could expire in the middle of a debug session,
to prevent that, just make sure to disable watchdog
on reset-end if current state is 'halted'.
Change-Id: Ib4f2a2321cba17cd8c56ca3ae63114a563a6de90
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2615
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
a later commit will implement a proper reset-init
handler to lock pll and configure ddr as we should.
Change-Id: I432cf28a5a944bfa83c20aed7298dbd29df30e38
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2614
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
According to AM4379 TRM [1], table 2-1 L3 Memory Map,
we have a total of 256KiB and there's no reason not to
use it all.
[1] http://www.ti.com/lit/ug/spruhl7b/spruhl7b.pdf
Change-Id: I117f2afe721bc4e3f0df304d3542e1a91aa69d12
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2611
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Since commit ec9ccaa288 (arm_adi_v5: make dap_lookup_cs_component()
traverse subtables and handle multicore) AM437x devices can't be used
with OpenOCD anymore. The reason is that dbgbase used to be set to zero
before that commit and that just happens to work with AM437x devices.
A more robust solution is to pass correct dbgbase when creating the
target, which this commit does.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Change-Id: Iaf2617804324de8094b25137943e08b84f14c75f
Reviewed-on: http://openocd.zylin.com/2602
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This should allow most of the existing configurations for older
versions to remain compatible without forcing the user to change his
or her config to explicitly select transport.
Also in some circumstances can remove the need to chain a "-c transport
select X" when building custom configs on the command line, which seems
like a common new user pitfall.
Change-Id: Ic87a38c0b9b88e88fb6d106385efce2f39381d3d
Suggested-by: Petteri Aimonen <jpa@git.mail.kapsi.fi>
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2551
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Valgrind-tested.
Comparison of flashing performance on an FRDM-KL25Z board running mbed
CMSIS-DAP variant, 5MHz clock, old driver:
wrote 28096 bytes from file demo.elf in 26.833590s (1.023 KiB/s)
verified 27264 bytes in 1.754972s (15.171 KiB/s)
this implementation:
wrote 28096 bytes from file demo.elf in 3.691939s (7.432 KiB/s)
verified 27264 bytes in 0.598987s (44.450 KiB/s)
Also tested "Keil ULINK-ME CMSIS-DAP" with an STM32F100 target, 5MHz
clock, results reading from flash, old driver:
dumped 131072 bytes in 98.445305s (1.300 KiB/s)
this implementation:
dumped 131072 bytes in 8.242686s (15.529 KiB/s)
Change-Id: Ic64d3124b1d6cd9dd1016445bb627c71e189ae95
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2356
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
Keep clocks running in low power modes. Stop watchdogs from interfering
with the debug session. Set up PLL and increase clock at reset init.
Change-Id: I984d2018f7d47a1042f1e12894563154fa7b566c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2196
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Initial Support for AT91SAM7A2 on Olimex SAM7-LA2 board.
The board seems not to be able to reset into halted mode, as srst is
connected to NRESET of the cpu (configured srst_pulls_trst).
JTAG RCLK is connected to CLK.
Tested with interface/ftdi/olimex-arm-usb-ocd-h.cfg.
Change-Id: I2bdd67e3683e45f1119c5850bad294aa107891d8
Signed-off-by: Arne Wichmann <arne.wichmann@gmail.com>
Reviewed-on: http://openocd.zylin.com/2318
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds configs for Alphascale asm9260t ARM based SoC and
Evaluation Kit based on this chip.
Change-Id: Id8d3a1ef204e3ae84540c2693e3d62650ba82f73
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2515
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The flash definition belongs in the target cfg. Add some working area
and suitable reset_config.
Make kx.cfg more similar to klx.cfg.
Disable rclk as it is dead slow and a fixed 1MHz clock seems to work.
Change-Id: I8328f179c3a33be64403da93616abb48651bdfe6
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2227
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This is a new driver for Silicon Laboratories SiM3 microcontroller
family, based on the work of Ladislav Bábel. The driver will try to
detect the type of MCU from the device id register, and if this
fails it will use the flash size from the flash bank command.
Driver added to the documentation and to the README.
TCL script added.
Tests:
* Hardware: SiM3C166 (pre-production) and SiM3U167
* Binary: 4kb, 197kb, 256kb
* Flash protect not tested
Change-Id: I701e0cf505ca8ad99be7f83543fe5055b2f65dcc
Signed-off-by: Andreas Bomholtz <andreas@seluxit.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2078
Tested-by: jenkins
Add configs for Atheros ar9331 MIPS based WiSoC and
board based on this chip: TP-LINK TL-MR3020
Change-Id: I9e99719bce4bbb28311f6e9cddb32288db6e7b91
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2519
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
adds flash support for Nuvoton M052, M054, M058, M0516 microcontrollers
into the mini51 driver, patch also adds support for programing LDROM,
flash data and flash config.
I've tested it on a M0516LBN microcontroller using an ST-LINK/V2:
1. removing security lock:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "init ; halt ; mini51 chip_erase; exit"
2. flashing:
openocd -f interface/stlink-v2.cfg -f target/m051.cfg -c "program file.hex"
Change-Id: I918bfbb42461279c216fb9c22272d77501a2f202
Signed-off-by: Pawel Si <stawel+openocd@gmail.com>
Reviewed-on: http://openocd.zylin.com/2426
Tested-by: jenkins
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Added support for the Cortex-M3 based TI low power RF SoC CC2538 and
the CC26xx family.
These chips need a start sequence for switching from cJTAG to JTAG
before being used with OpenOCD, this is done in the tcl proc
ti_cjtag_to_4pin_jtag in the ti-cjtag.cfg config.
The configs for CC2538 and CC26xx run the start sequence on post-reset
event and set the ICEPick IDCODE in the data register for OpenOCD to
read, this is done so that every time OpenOCD resets the device, it
will enable JTAG.
Change-Id: I7db620211c0e7e03fad59d24fe31d23a9cdcfedc
Signed-off-by: Jacob Palsson <jaaacke@gmail.com>
Reviewed-on: http://openocd.zylin.com/2232
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds support for Silicon Labs (formerly Ember) EM357
and EM358 chips and derivatives.
Change-Id: Ie63aed95a2f4ef1a6b955e301a51b4de1b3a5462
Signed-off-by: Ed Beroset <beroset@ieee.org>
Reviewed-on: http://openocd.zylin.com/2470
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
New NOR flash driver was derived from stm32lx.
Procedure ocd_process_reset_inner is overriden in psoc4.cfg
to handle reset halt and system ROM peculiarities.
Change-Id: Ib835324412d106ad749e1351a8e18e6be34ca500
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2282
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds a trivial config for LPC8xx chips based on the already
existing infrastructure in lpc1xxx.cfg.
Change-Id: I7384df1f3c2e3e8ab767319728db5c4f8149480f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2464
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
It depends on the particular target whether it can work with SRST
asserted or not, so this belongs to the target config rather than the
board config.
Also, this allows for simple
openocd -f myboard.cfg -c "reset_config connect_assert_srst"
command to be used whenever a user feels a need to connect to an
unresponsive target.
Change-Id: I3d8da9ae47088fc0c75a20bfdd20074be1014de0
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2459
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
So remove it from all the configs, it's misleading, and leads to cargo
culting of config files.
Change-Id: I2b77e60d5e96f9759c7c9fc91b20e73be2e95d9a
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2446
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This should have been corrected earlier with the split of l1/l0 code
apart.
Change-Id: I87b94a310ae7e76318554a9cd2705348a942d58b
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2447
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup. It has no endian options, no boundary scan.
Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose. The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.
Tested on STM32L053 Discovery and STM32L151 Discovery.
Has _not_ been tested with jtag on L1.
Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
Fix script parse error, when using JTAG, introduced in
commit 0187ced9ed
Add several BS TAPIDs with comments about ST documentation.
Change-Id: I8d0370b244ccaf7ea0dbe1919bfad1915f7317d4
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Reviewed-on: http://openocd.zylin.com/2376
Tested-by: jenkins
Reviewed-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since all F4 parts have an internal HSI providing 16MHz, it's safe to
use 2MHz JTAG frequency by default.
Change-Id: I2702d5a1d642d4acd4af2db54c028949132c6900
Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2383
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add CPUTAPID for stm32 L0xx mcu devices. Using -expected-id to
add the new id with the id for L1xx devices. This for reduce the
duplicated code.
Change-Id: I48bd230884ecf38fa200c620b547bdf3b5f59132
Signed-off-by: Rémi PRUD'HOMME <prudhomme.remi@gmail.com>
Reviewed-on: http://openocd.zylin.com/2315
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Remove this underutilized feature. Despite the fact that a lot of configs
specifies a arbitrary "variant", only the xscale target actually defines
any.
In the case of xscale, the use of -variant is dubious since
1) it's used as a redundant irlen specifier,
2) it carries a comment that it doesn't really need it and
3) only two xscale configs even specify it.
If there's a future target that needs a variant set, a target specific
option could be added when needed.
Change-Id: I1ba25a946f0d80872cbd96ddcc48f92695c4ae20
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2283
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since now auto-detection for flash size works nicely, there's no
reason to keep numerous configs around.
Change-Id: If0cbc37985abf17ef7c1f7d0688e76500fac228f
Signed-off-by: Vanya Sergeev <vsergeev@gmail.com>
Reviewed-on: http://openocd.zylin.com/1960
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds config to allow JTAG debugging of an ARM core of a modern
hybrid SoC by Research Centre "Module"
(http://www.module.ru/en/company/). К1879ХБ1Я is targetted at set-top
boxes and other multimedia equipment, the official SDK is Linux-based.
Change-Id: Ib2ae5784d25699f952682e66b025a3f677a76d5d
Signed-off-by: Бурага Александр <dtp-avb@yandex.ru>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2272
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This is for mx6q TO1.1.
Change-Id: Id6af2ed232fc19be9bf49eb6d2df0004c6668698
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2253
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
According to Nordic Semiconductor Product Anomaly Notice (document
NRF51822-PAN), item 16, some revisions of nRF51822 sometimes reset
without all RAM blocks enabled. This was noted on NRF51822-QFAA rev
CA/C0, only 8KiB of memory was accessible.
This patch turns on all RAM following a debugger induced reset
(matches specified behaviour.)
Change-Id: I4f8be4ec3d1271da7fe5bc9a084fdcb2968535bb
Signed-off-by: Angus Gratton <gus@projectgus.com>
Reviewed-on: http://openocd.zylin.com/2202
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This should allow to share common configs for both regular access and
high-level adapters.
Use the newly-added functionality in stlink and icdi drivers, amend
the configs accordingly.
Runtime-tested with a TI tm4c123g board.
Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
[gus@projectgus.com: context-specific deprecation warnings]
Signed-off-by: Angus Gratton <gus@projectgus.com>
[andrew.smirnov@gmail.com: additional nrf51.cfg mods]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1664
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
I looked through all the target configs after stripping comments and
such from them with sed to see what jtag-specific commands can appear
first, and it looks like all the meaningful combinations should be
covered.
Change-Id: I8d543407b7f4ac8aca7354ecd50e841c8a04d5f3
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2179
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
SAM4L requires additional steps to be taken right after SYSRESETREQ is
issued in order to function robustly:
- CMSIS-DAP DAP driver needs to explicitly check for sticky bit
errors since it is possible for adapter to perform successful
write opration, report no errors and then, under the hood, do
some other things that will result in sticky bit being set.
- Debugger needs to wait for security system to finish
intialization and assert CDBGPWRUPACK before proceeding
This change is related to commit http://openocd.zylin.com/#/c/1995/
Change-Id: I741c95a809bfd60d930cec9482239e4796a62326
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2088
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
fm3 flash driver needs to know which chip variant is used.
This fixes "unknown fm3 variant: mb9bf500.cpu" error if the config is
used as is.
Change-Id: I500fcfb413f23ee246678cec5bd19d14139a28e2
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2160
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This isn't needed nor a recommended practice now, was a simple
copy/paste from amdm37x.cfg anyhow.
Change-Id: I064226dc859d7563cfad945b577279fc37448645
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2068
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Maximum frequency wasn't tested on hardware but the docs seem to be
quite explicit and do not mention any restrictions for that.
Change-Id: Idcf58df5358d06525e683f07c76eedad8f0b292d
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2120
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This patch adds Micrel's KS869x target. The configuration was taken from
http://www.mmnt.net/db/0/0/www.micrel.com/ethernet/8695 - Micrel's
FTP server i.e. their OpenOCD 7.0 package.
The only change compared to the original file is the removal of
reset configuration, as it belongs to the board configuration.
Change-Id: Ic8509aa5fe5ce3166a3129e1c055280a3b2b9312
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-on: http://openocd.zylin.com/2125
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Old version of the code had several problems, among them are:
* Located in a generic ADI source file instead of some Kinetis
specific location
* Incorrect MCU detection code that would read generic ARM ID
registers
* Presence of SRST line was mandatory
* There didn't seem to be any place where after SRST line assertion
it would be de-asserted.
* Reset was asserted after waiting for "Flash Controller Ready" bit
to be set, which contradicts official programming guide AN4835
* Mass erase algorithm implemented by that code was very strange:
** After mass erase was initiated instead of just polling for the
state of "Mass Erase Acknowledged" bit the code would repeatedly
initiate mass erase AND poll the state of the "Mass Erase
Acknowledged"
** Instead of just polling for the state of "Flash Mass Erase in
Progress"(bit 0 in Control register) to wait for the end of the
mass erase operation the code would: write 0 to Control
register, read out Status register ignoring the result and then
read Control register again and see if it is zero.
* dap_syssec_kinetis_mdmap assumed that previously selected(before
it was called) AP was 0.
This commit moves all of the code to kinetis flash driver and
introduces three new commands:
o "kinetis mdm check_security" -- the intent of that function is to be used as
'examine-end' hook for any Kinetis target that has that kind of
JTAG/SWD security mechanism.
o "kinetis mdm mass_erase"" -- This function removes secure status from
MCU be performing special version of flash mass erase.
o "kinetis mdm test_securing" -- Function that allows to test securing
fucntionality. All it does is erase the page with flash security settings thus
making MCU 'secured'.
New version of the code implements the algorithms specified in AN4835
"Production Flash Programming Best Practices for Kinetis K-
and L-series MCUs", specifically sections 4.1.1 and 4.2.1.
It also adds KL26 MCU to the list of devices for which this security
check is performed. Implementing that algorithm also allowed to simplify
mass command in kinetis driver, since we no longer need to write security
bytes. The result that the old version of mass erase code can now be
acheived using 'kinetis mdm mass_erase'
Tested on accidentally locked FRDM-KL26Z with KL26 Kinetis MCU.
Change-Id: Ic085195edfd963dda9d3d4d8acd1e40cc366b16b
Signed-off-by: Andrey Smrinov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2034
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Add configuration file for General Plus GP326XXXA series. Tested on
GP326833A on GPC-1737B board.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: I1ad0e22598b01317bbc823870a7a262e9192c595
Reviewed-on: http://openocd.zylin.com/2058
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
The TI TMS470 and TMS570 series of processors are BE-32 processors,
despite BE-32 not being supported by ARM in the Cortex-R4 core. TI
hacked in BE-32 support, which requires odd swizzling in OpenOCD to
make memory reads and writes function correctly. In particular,
without this change, OpenOCD word reads and writes had the bytes
reversed, and halfword and byte packed reads were reading garbage.
In my testing, this change fixes these problems.
Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74
Signed-off-by: Seth LaForge <sethml@google.com>
Reviewed-on: http://openocd.zylin.com/2064
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Also add the board to the firmware recovery script.
Change-Id: I4f9c895dae171df7249e3b1c0563b288518b9fe0
Signed-off-by: Lee Bowyer <lee@sodnpoo.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2097
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
SoftDevice stack ihex binary, provided by Nordic expects being able to
write data necessary for its correct operation at the adresses inside UICR.
This patch exposes UICR region of flash as a second bank on the MCU to
facilitate that.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Change-Id: Idbc140b8de027f60655f78043877b7c054eb06f9
Reviewed-on: http://openocd.zylin.com/2013
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This adds support for the am43xx SoC and the AM437x GP EVM and AM438x
ePOS EVM.
Change-Id: I09cbb09072f38e0e08fdd520dedb6e67d45056be
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2047
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
instead of replicating icepick_d_tapenable in many of TI's newer
platforms, we can move to icepick.cfg and just call it from board TCL
configuration file. This is similar to the C but has a few changes we
need to make.
Change-Id: I0ab48005ccd66cd5b67b919fb5e3b462288f211d
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-on: http://openocd.zylin.com/2030
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
From testing this target does not seem to support using SYSRESETREQ, change
the default to the safe VECTRESET.
This target also has other reset issues (srst not working) that will be
addressed in another patch.
Change-Id: Icfc78347dc71aa3a062ddea63190a818d7fbc760
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1995
Tested-by: jenkins
Reviewed-by: Angus Gratton <gus@projectgus.com>
Atmel's SAM3 and SAM4 processor families are very close to each other
in many respects. However, so far, only the SAM4 target script
contained the magic to allow using SWD, while SAM3 was tied to JTAG
only. This e.g. prevented the CMSIS-DAP driver from accessing SAM3
devices as it only uses SWD transport (by now).
The patch pulls all the things from the SAM4 target script that are
also applicable to SAM3 devices. With the patch, an Atmel CMSIS-DAP
debugger (Atmel-ICE) was proven to be able to successfully attach to a
SAM3S-EK evaluation kit. I also cross-checked that accessing through
a SAM-ICE (Segger J-Link) still works with the patch.
Change-Id: I20dafbff8e1e9f967da950e48a56205586eeef8d
Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Reviewed-on: http://openocd.zylin.com/2046
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Add support for Broadcom's dual A9 mobile SoC and its reference board.
Change-Id: Ia145b120043bddc89c44726066023154ae390788
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-on: http://openocd.zylin.com/1926
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
flash: at91sam4: add support for the SAMG53 family (this also covers the
SAMG51). The SAMG5x parts have an EEFC (enhanced embedded flash controller)
which seems to be identical to the EFC that the sam4 driver supports.
Add a script for the Xplained Pro G53 board, this has the onboard CMSIS-DAP
debugger and a SAMG53N19. Tested on this board and chip combination.
Change-Id: I12af50402cd2069b3c7380d92e6fe54816d6c045
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-on: http://openocd.zylin.com/1974
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h
Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Originally the LPC17xx user guide (UM10360 Rev 2) stated that SYSRESETREQ
was not supported, so this was the default cortex_m reset mode.
Rev 3 of the same user guide states that it is now supported.
This has been verified on a LPC1768 mbed platform, previously I have not
tested this functionality.
Change-Id: I4858248903981a1c93ce75016e67c9e02702fcc5
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1892
Tested-by: jenkins
Reviewed-by: Jörg Fischer <turboj@gmx.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Andreas Färber
Nemui Trinomius
Ivan Buliev
Radek Dostal
Jiri Kastner
Alex Ray
Spencer Oliver
Paul Fertser
Tomas Vanek
Ed Beroset
Felipe Balbi
Angus Gratton
Uwe Bonnes
Andreas Fritiofson
Arne Wichmann
Oleksij Rempel
Andreas Bomholtz
Pawel Si
Jacob Palsson
Karl Palsson
Karl Palsson
Juha Niskanen
Rémi PRUD'HOMME
Vanya Sergeev
Бурага Александр
Andrey Skvortsov
Andrey Smirnov
Franck Jullien
Tom Rini
Yegor Yefremov
Seth LaForge
Lee Bowyer
Tim Sander
Jörg Wunsch
Tim Kryger
Andrey Yurovsky
Fatih Aşıcı
Adrian Burns