Scan-build is unable to detect that 'target->dbg_msg_enabled' does
not change across the function cortex_m_fast_read_all_regs().
It incorrectly assumes that it can be false at the first check (so
'dcrdr' get not assigned) and it is true later on (when 'dcrdr'
get used).
This triggers a false positive:
src/target/cortex_m.c:338:12: warning:
3rd function call argument is an uninitialized value
[core.CallAndMessage]
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
Use a local variable for 'target->dbg_msg_enabled' so scan-build
can track it as not modified.
While there, change the type of 'target->dbg_msg_enabled' to
boolean as there is no reason to use uint32_t.
Change-Id: Icaf1a1b2dea8bc55108182ea440708ab76396cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8391
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U53/U54x devices are similar to U57/U58x devices
with 2 flash banks up to 256 KB each
Change-Id: I774ef0df4dddac5f06bbfc2e6c3fc2e628d2249e
Signed-off-by: FBOSTM <fedi.bouzazi@st.com>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7515
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
STM32U59/U5Ax devices are similar to U57/U58x devices
with 2 flash banks up to 2 MB each
while at there update STM32U57x/U58x revisions
Change-Id: I7e5c1700acf8c9fda34f660c9274bfd8bcb1381b
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6875
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
As defined in `target/target.h`, `coreid` is the index of the target on
the TAP, so, if an SMP group includes targets from multiple TAPs, it can
not be used as the base for `threadid`.
Change-Id: Ied7cfa42197aaf4908ef6628c6436f28d4856ebe
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7957
Tested-by: jenkins
Reviewed-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Direct memory driver swd native configuration for am62a7, am62p and
J722S SoCs. All three share common memory map for the debug address
map, so there is a strong reuse. However, introduce board file
specific to the board to allow users to directly get started.
Change-Id: I5609925a2e9918fd4c91d9fd40fbee98de27fdbc
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8283
Tested-by: jenkins
Reviewed-by: Vaishnav M A <vaishnav@beagleboard.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Use a command group 'tcl' with subcommands instead of individual
commands with 'tcl_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I1efd8a0e2c1403833f8cb656510a54d5ab0b2740
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8344
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Use a command group 'gdb' with subcommands instead of individual
commands with 'gdb_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I037dc58554e589d5710cf46924e0a00f863aa300
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8336
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Added FT4232HA varianet of FTDI's FT4232H which has a different bcd.
Also added default PID/VID for the FT4243HA to contrib/60-openocd.rules.
And added default PID/VIDs for FTDI's HP ICs to contrib/60-openocd.rules
as this wasn't done previously.
BugLink: https://sourceforge.net/p/openocd/tickets/410/
Change-Id: Ia84b566aa004332d3f7815a3d22ac37eee4f522a
Signed-off-by: Jonathan Forrest <jonyscathe@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8225
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The function str_to_buf() was too benevolent and did
not perform sufficient error checking on the input
string being parsed. Especially:
- Invalid numbers were silently ignored.
- Out-of-range numbers were silently truncated.
The following commands that use str_to_buf()
were affected:
- reg (when writing a register value)
- set_reg
- jtag drscan
This pull request fixes that by:
- Rewriting str_to_buf() to add the missing checks.
- Adding function command_parse_str_to_buf() which can
be used in command handlers. It parses the input
numbers and provides user-readable error messages
in case of parsing errors.
Examples:
jtag drscan 10 huh10
- Old behavior: The string "huh10" is silently
converted to 10 and the command is then executed.
No warning error or warning is shown to the user.
- New behavior: Error message is shown:
"'huh10' is not a valid number"
reg pc 0x123456789
Assuming the "pc" is 32 bits wide:
- Old behavior: The register value is silently
truncated to 0x23456789 and the command is performed.
- New behavior: Error message is shown to the user:
"Number 0x123456789 exceeds 32 bits"
Change-Id: I079e19cd153aec853a3c2eb66953024b8542d0f4
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8315
Tested-by: jenkins
Reviewed-by: Marek Vrbka <marek.vrbka@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The driver code works reliably, no need to use assert() everywhere.
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Idb1942bfd31d370a74610b8a8836bc2e64370557
Reviewed-on: https://review.openocd.org/c/openocd/+/8324
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
nrf5_auto_probe() always re-probed chip hardware to
get flash geometry.
Introduce nrf5_probe_chip() and move chip related probing to it.
Save all flash parameters needed for bank setup to struct nrf5_info.
Introduce nrf5_setup_bank() and move bank setup code to it.
Call both chip probe and bank setup unconditionally from nrf5_probe():
in case of manual issuing 'flash probe' command, we should refresh actual
values from the device.
Call chip probe and bank setup only if not done before from
nrf5_auto_probe().
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: Ib090a97fd7a41579b3d4f6e6634a5fdf93836c83
Reviewed-on: https://review.openocd.org/c/openocd/+/8322
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ARM documentation for Cortex-M reports the field 'implementer' in
the register CPUID.
OpenOCD used the miss-spelled 'implementor'. Fix it!
Change-Id: I854d223971ae7a49346e1f7491c2c0415f5e2c1d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8318
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Add Cortex-M52 to the list of known Cortex-M implementations to
allow detection of the core.
Values checked against the ARM document "Arm China Cortex®-M52
Processor Technical Reference Manual" 102776_0002_06_en.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: Id0bde8a0476f76799b7274835db9690f975e2dd6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8317
Tested-by: jenkins
The detection of Cortex-M STAR-MC1 was introduced with [1], at a
time when OpenOCD was only checking the field PartNo of the CPUID
register.
Later-on [2], OpenOCD extended the check to the field implementer
of CPUID register. The value for ARM (0x41) implementer was used
to all the Cortex-M, but no feedback for STAR-MC1 was available. A
comment reporting the possible mismatch was added.
As reported on OpenOCD mailing-list, the technical reference manual
for STAR-MC1 is now available [3] and it reports the implementer
as ARM China (0x63) [3].
Fix the STAR-MC1 implementer accordingly.
Reported-by: Joseph Yiu <Joseph.Yiu@arm.com>
Change-Id: I8ed1064a847b73065528ee7032be967b5c58b431
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Link: [1] 7dc4be3157 ("target/arm: Add support with identify STAR-MC1")
Fixes: [2] 05ee889155 ("target/cortex_m: check core implementor field")
Link: [3] https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160
Reviewed-on: https://review.openocd.org/c/openocd/+/8316
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Use a command group 'hla' with subcommands instead of individual
commands with 'hla_' prefix.
The old commands are still available to ensure backwards compatibility,
but are marked as deprecated.
Change-Id: I612e3cc080d308735932aea0f11001428eadc570
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8335
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add space around math operators.
Change-Id: I50fce3da283a78ba02bf70b6a752f7bf778d79f5
Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7585
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Working on an old local git repository, the git sub-modules could
have been set before last changes in .gitmodules.
The script 'bootstrap' does not update the url of the repositories
and this can cause the script to fail.
Add 'git submodule sync' to the script to update the url of the
repositories.
While there, fuse 'git submodule init' and git submodule update'
in a single command.
Reported-by: Karl Hammar <karl@aspodata.se>
Change-Id: I61412f804dbbb7a843aa009139ddb4b8e71beefb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8375
Tested-by: jenkins
Remove the outdated option '--pipe' and bring the description of OpenOCD
up to date without focus on JTAG only.
Change-Id: If52e936a366dde21c1dd514bd3960d100b540e77
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8347
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The list of authors and contributors is not maintained and outdated for
years now. Refer to the source code and Git history instead of keeping a
separate list.
Change-Id: I9a92e8e0d5073b56030bc36086b76e28de96389f
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8346
Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The flag '-coreid' is used by the command 'target create' to
specify the debug controller of the target, either in case of a
single debug controller for multiple CPU (e.g. RISC-V harts) or
in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP
cluster).
It is also currently used to specify the CPU ID in a SMP cluster,
but this is going to be reworked.
This flag has no effects on Cortex-M; ARM specifies that only one
CPU Cortex-M can occupy the DAP access port by using hardcoded
addresses.
The flash driver 'psoc6' uses the flag '-coreid' to detect if the
current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2
in the SoC.
There are other ways to run such detection, without using such
unrelated '-coreid' flag, e.g. using the AP number or the arch
type of the target.
Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4
(ARM_ARCH_V7M).
Drop the flags '-coreid' from the psoc6 configuration file.
Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8128
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Add to the command 'target create' the description for the flags
'-dbgbase' and '-coreid'.
Report that '-coreid' is currently used for purposes other than
CPU detection/examination, and that such uses are going to be
re-considered.
Change-Id: I25c839e3653101234c5862ce9da77019a5bb3249
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8129
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
When an asynchronous exception occurs at the same time
as a breakpoint event (either hardware breakpoint or software breakpoint),
it is possible for the processor to halt at the beginning of the
exception handler instead of the instruction address pointed
by the breakpoint.
During debug entry in exception handler state and with BKPT bit set
as the only break reason in DFSR, check if there is a breakpoint, which
have triggered the debug halt. If there is no such breakpoint,
resume execution. The processor services the interrupt and
halts again at the correct breakpoint address.
The workaround is not needed during target algo run (debug_execution)
because interrupts are disabled in PRIMASK register.
Also after single step the workaround resume never takes place:
the situation is treated as error.
Link: https://developer.arm.com/documentation/SDEN1068427/latest/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769
Reviewed-on: https://review.openocd.org/c/openocd/+/8332
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Liviu Ionescu
Make sure raspberrypi-native.cfg cannot be used on RPi5.
Add raspberrypi5-gpiod.cfg which uses linuxgpiod adapter driver.
Issue a warning if PCIe is in power save mode.
While on it, re-format warnings issued from Tcl to look similar
to LOG_WARNING() output.
Change-Id: If19b0350bd5fff83d9a0c65999e33b161fb6957a
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8333
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Most of the work is already done by [1].
Remove few more '_s' suffix and also fix some comment referring to
the old name of the struct.
Link: https://review.openocd.org/c/openocd/+/8340
Change-Id: Ifddc401c3b05e62ece3aa7926af1e78f0c4a671e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8341
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The output "gdb port disabled" is confusing without reference to the
target. Use LOG_TARGET_INFO() to output the target name.
While at it, use LOG_TARGET_xxx() for all log statements where the
target name is already used.
Change-Id: I70b134145837db623e008a4a6c0be0008d9a0d87
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8313
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Changes affect the function remote_bitbang_fill_buf.
When read_socket returns 0, socket reached EOF and there is
no data to read. But if request was blocking, the caller
expected some data. Such situations should be treated as ERROR.
Change-Id: I02ed484e61fb776c1625f6e36ab14c85891939b2
Signed-off-by: Timur Golubovich <timur.golubovich@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8325
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Commit f9509c92db ("itm: rework itm commands before 'init'")
ignores the default enable of ITM channel 0, that is applied when
no 'itm port[s]' is issued.
Call armv7m_trace_itm_config() unconditionally to handle it.
Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Paul Fertser <fercerpav@gmail.com>
Fixes: f9509c92db ("itm: rework itm commands before 'init'")
Reviewed-on: https://review.openocd.org/c/openocd/+/7900
Reviewed-by: <post@frankplowman.com>
Tested-by: jenkins
The register SPSR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL1
or through OpenOCD command
reg SPSR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8276
Tested-by: jenkins
The register ESR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL1
or through OpenOCD command
reg ESR_EL1
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8275
Tested-by: jenkins
The register ELR_EL1 is accessible and it's content is relevant
only when the target is in EL1 or EL2 or EL3.
Without this patch, an error:
Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL1
or through OpenOCD command
reg ELR_EL1
Detect the EL and return error if the register cannot be accessed.
Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8274
Tested-by: jenkins
The register SPSR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns SPSR_EL1. Debugger should not
mix the real SPSR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL2
or through OpenOCD command
reg SPSR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8273
Tested-by: jenkins
The register ESR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix
the real ESR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL2
or through OpenOCD command
reg ESR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8272
Tested-by: jenkins
The register ELR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix
the real ELR_EL2 with the virtual register.
Without this patch, an error:
Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL2
or through OpenOCD command
reg ELR_EL2
Detect the EL and return error if the register cannot be accessed.
Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8271
Tested-by: jenkins
The register SPSR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL3
or through OpenOCD command
reg SPSR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8270
Tested-by: jenkins
The register ESR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ESR_EL3
or through OpenOCD command
reg ESR_EL3
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Drop the FIXME comment on Aarch32 case, as the register exists in
Aarch64 only.
Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8269
Tested-by: jenkins
The register ELR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Without this patch, an error:
Error: Opcode 0xd53e4020, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $ELR_EL3
or through OpenOCD command
reg ELR_EL3
Detect the EL and return error if the register cannot be accessed.
Change-Id: I545abb196e5c34e462c7e5d5d3ec952e588642da
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8268
Tested-by: jenkins
The command 'gdb_report_register_access_error' is used to silence
errors while reading registers and not reporting them to GDB.
Nevertheless, the error is printed by a LOG_ERROR() in armv8_dpm.
Change the message to LOG_DEBUG().
It will still cause the error to be propagated and eventually
printed by the caller (e.g. by the command 'reg').
Change-Id: Ic0db74fa28235d686ddd21a5960c52ae003e0931
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8267
Tested-by: jenkins
These functions are today always called with non-NULL parameter
regval, so the actual check is not needed.
Anyway, for any future code change, check the parameter at the
entry of the functions and return error if it is not valid.
Simplify the check to assign the result value and align the code
of the two functions.
Change-Id: Ie4d98063006d70d9e2bcfc00bc930133caf33515
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8266
Tested-by: jenkins
Use LOG_TARGET_ERROR() to print the error messages and additionally add
a reference to the related target.
Change-Id: I06722f3911ef4034fdd05dc9b0e2571b01b657a4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8314
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
cortex_m_poll_one() detects reset testing S_RESET_ST sticky bit.
If the signal comes unexpectedly, poll must return TARGET_RESET state.
On the contrary in case of polling inside of an OpenOCD reset command,
TARGET_RESET has been has already been set and we need to get out of
it as quickly as possible.
The original code needs 2 polls: the first clears S_RESET_ST
and keeps TARGET_RESET state, the current TARGET_RUNNING or TARGET_HALTED
is reflected as late as the second poll is done.
Change the logic to keep in TARGET_RESET only when necessary.
See also [1]
Link: [1] 8284: tcl/target: ti_cc3220sf: Use halt for CC3320SF targets | https://review.openocd.org/c/openocd/+/8284
Fixes: https://sourceforge.net/p/openocd/tickets/360/
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Change-Id: I759461e5f89ca48a6e16e4b4101570260421dba1
Reviewed-on: https://review.openocd.org/c/openocd/+/8285
Tested-by: jenkins
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Remove list of id codes for all families.
Maintain a list with id, bscan-length and check position
in the tcl config files for each family.
The Intel FPGA Driver option 'family' is not otional anymore.
Change-Id: I9a40a041069e84f6b4728f2cd715756a36759c89
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/8083
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Antonio Borneo
Tarek BOCHKATI
Tarek BOCHKATI
Evgeniy Naydanov
Nishanth Menon
Marc Schink
Jonathan Forrest
Jan Matyas
Tomas Vanek
Ian Thompson
Mark Zhuang
Timur Golubovich
Daniel Anselmi
George Voicu