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target: aarch64: access reg ESR_EL3 only in EL3 

The register ESR_EL3 is accessible and it's content is relevant
only when the target is in EL3.
Plus, the register is 64 bits wide.

Without this patch, an error:
	Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
        x/p $ESR_EL3
or through OpenOCD command
        reg ESR_EL3

Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Drop the FIXME comment on Aarch32 case, as the register exists in
Aarch64 only.

Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8269
Tested-by: jenkins
This commit is contained in:
Antonio Borneo 2024-05-14 10:03:09 +02:00
parent 8c75e47603
commit 2306809160
1 changed files with 17 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/target/armv8.c
View File

@ -342,9 +342,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
value_64 = value;
break;
case ARMV8_ESR_EL3:
retval = dpm->instr_read_data_r0(dpm,
ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value);
value_64 = value;
if (curel < SYSTEM_CUREL_EL3) {
LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
retval = ERROR_FAIL;
break;
}
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS(SYSTEM_ESR_EL3, 0), &value_64);
break;
case ARMV8_SPSR_EL1:
retval = dpm->instr_read_data_r0(dpm,
@ -469,9 +473,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
ARMV8_MSR_GP(SYSTEM_ESR_EL2, 0), value);
break;
case ARMV8_ESR_EL3:
value = value_64;
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value);
if (curel < SYSTEM_CUREL_EL3) {
LOG_DEBUG("ESR_EL3 not accessible in EL%u", curel);
retval = ERROR_FAIL;
break;
}
retval = dpm->instr_write_data_r0_64(dpm,
ARMV8_MSR_GP(SYSTEM_ESR_EL3, 0), value_64);
break;
case ARMV8_SPSR_EL1:
value = value_64;
@ -575,7 +583,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
ARMV4_5_MRC(15, 4, 0, 5, 2, 0),
&value);
break;
case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
retval = ERROR_FAIL;
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
@ -711,7 +719,7 @@ static int armv8_write_reg32(struct armv8_common *armv8, int regnum, uint64_t va
ARMV4_5_MCR(15, 4, 0, 5, 2, 0),
value);
break;
case ARMV8_ESR_EL3: /* FIXME: no equivalent in aarch32? */
case ARMV8_ESR_EL3: /* no equivalent in aarch32 */
retval = ERROR_FAIL;
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
@ -1534,7 +1542,7 @@ static const struct {
{ ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_ESR_EL3, "ESR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
{ ARMV8_ESR_EL3, "ESR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
NULL},
{ ARMV8_SPSR_EL3, "SPSR_EL3", 32, ARMV8_64_EL3H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
NULL},