When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.
To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.
Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart. Those assertions
aren't sane very early in examine, so I avoid them.
Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled". This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting. This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.
Smoketest indicates everything is working more or less as before.
When gcc isn't optimizing well, it might not realize that it's not
possible to return fd without initializing it, and then the build fails
due to -Werror.
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558
Extended and revised version of my original patch submitted by Dmytro
here: http://openocd.zylin.com/#/c/3390
This driver is using pure SPI mode, so the flash base address is not
used except some flash commands (e.g. "flash program") need it to
distinguish the banks.
Example config with all 3 chip selects:
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
Example usage:
> flash probe flash0
Found flash device 'win w25q128fv' (ID 0x001840ef)
flash 'ath79' found at 0x00000000
> flash probe flash1
No SPI flash found
> flash probe flash2
No SPI flash found
> flash banks
> flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000
reading 4096 bytes from flash @0x00000000
wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset
0x00000000 in 28.688066s (0.139 KiB/s)
Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8
Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de>
Reviewed-on: http://openocd.zylin.com/3612
Tested-by: jenkins
Reviewed-by: Dmytro <dioptimizer@hotmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
For some targets (like nrf51) sysfs driver is too slow. This
patch implements memory maped driver for IMX processors.
Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should
work on any NXP IMX CPU.
Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7
Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com>
Reviewed-on: http://openocd.zylin.com/4106
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This means I don't know what hart to look at, so I might as well
invalidate the register cache. Without this, you might get stale
registers the first time you ask for them.
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode. With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
This patch adds a driver for the SWD-only Cypress KitProg
programmer/debugger.
Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5
Signed-off-by: Forest Crossman <cyrozap@gmail.com>
Reviewed-on: http://openocd.zylin.com/3221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
There is no need to implement scan code in functions
mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32().
Impcode/idcode saved in ejtag.info.
Reorder the code in the callers of this functions.
Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170
Signed-off-by: Salvador Arroyo <salvador@telecable.es>
Reviewed-on: http://openocd.zylin.com/4003
Tested-by: jenkins
Reviewed-by: Peter Mamonov <pmamonov@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Breakpoint setting based on length (kind) only.
Added 16bit aligned 32bit software breakpoints
support and same filtering before setting
breakpoint.
Set the required isa bit in hardware breakpoints.
Drop the isa bit in software breakpoints.
Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4124
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Read and save configuration registers, up to 4.
Config3 holds the micromips implementation info.
Added isa implementation info to mips32_common.
Added isa filter to avoid common mistakes, but only
if one isa mode is implemented.
When resuming the isa requested is set if more than
one isa mode is implemented.
Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4123
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Needed to run in micromips mode. Seems that if an isa
is supported in debug mode it also supported in kernel
mode. The contrary is not true.
Change-Id: I1feb8e2c376f4db97089f05c20bc0cd177208fb3
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4033
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Micromips is 16bit oriented, branch and jumps are
16 bit based. The upper half 16bits of a 32bit instruction
with the major opcode, must go first in the instruction
stream, hence the SWAP16 macro and swap16 array function,
needed if the code is written as 32 bit word in little endian
cores. Endianess info added to ejtag_iinfo. Pointer to
ejtag_info and isa field added to pracc context.
MIPS32 code are renamed to MIPS32_ISA_...
To select the isa, the new code has an additional isa parameter
(1 for micromips, 0 for mips32).
In JR instruction the isa bit must be set to execute
micromips code.
The suffix u is added to the OP codes to avoid signed/unsigned
comparison errors and to make sure the right shift is
performed logically.
The isa in debug mode is updated in the poll function.
Code for miniprograms, in kernel mode, need to be converted.
CFI code only for mips32.
Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4032
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Only reencoded MIPS32 instructions. Added some instructions
for crc code. Micromips isa in debug mode is only needed for
pic32mm cores. Pic32mz seems that only works with MIPS32
isa when in debug mode.
Change-Id: I07059e153a7000ea9204f20b6b37edf6a7623455
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4022
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This option is needed, for example, when exiting
debug mode in bmips targets. The last instruction
is a NOP, not a DERET. When working in async mode
this check is not done, mips32_pracc_queue_exec() pass
the parameter to mips32_pracc_exec() and never use it.
Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4021
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
If max_code is reached realloc memory. If fails to realloc
the error is propagated and every call to pracc_add() returns
immediately. The exec function logs the error.
Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4020
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
pracc_list points to an array with code in the lower half
and addr in the upper half. Change it to a struct with
an instruction field and an address field.
Requiered to make reallocation easier.
As a side effect the code is less quirky.
Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4019
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
MacOSX tool chain defines __unused in "sys/cdefs.h", causing a collision.
Remove the local define to avoid polluting the compilers internal
symbol namespace.
Change-Id: I16370c4518e6aeec482dd689e7db80628f846ee3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4118
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt. This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports. This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around. The changes are:
* You can pass "-rtos riscv" to the target in OpenOCD's configuration
file, which enables multi-hart mode. This uses OpenOCD's RTOS
support to control all the harts from the debug module using commands
like "info threads" in GDB. This support is still expermental.
* There is support for RV64I, but due to OpenOCD limitations we only
support 32-bit physical addresses. I hope to remedy this by rebasing
onto the latest OpenOCD release, which I've heard should fix this.
* This matches the latest draft version of the RISC-V debug spec, as of
April 26th. This version fixes a number of spec bugs and should be
close to the final debug spec.
Less code and probably cleaner.
Don't check if it is ever ERROR_OK.
Change-Id: I1045b58fd4542ec24430332f49679364ae97b1dc
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4018
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Implement it as a function, the code was already in. Added optimize
option.
Change-Id: Ib9ad3f00d6c4f0b91c4e4960a50ec8d102f4e333
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4017
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
In most of the cases there is no need to request execution,
the check for a new pracc access already does it.
Requesting execution if not needed makes execution slower and
code larger due the additional checks.
Reduce code in fasdata transfer function.
Call for execution when exiting debug.
Change-Id: I3b45f6d1f62da5fad3e3db84f82a9299b16e1bd9
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4010
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Struct mips32_pracc_context no more in use.
In current code cp0 reg/sel do not requires special handling.
In sync mode ctx.store_count not used, drop check.
In fasdata transfer function use mips32_pracc_read_ctrl_addr()
to reduce code.
Change-Id: Ibd4cfa5a44ebc106ed0db042f4e54a2e0b3d43cb
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4007
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
With this patch OpenOCD shuts down properly when errors occur in the
server instead of just calling exit().
Change-Id: I2ae1a6153dafc88667951cab9152941cb487be85
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3223
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Will be used later, allow queuing all needed scans in a pracc
access. This makes faster execution with ftdi based adapters
working in sync with pracc.
Added now because the overall code is shorter.
Change-Id: Ib32b89307b75785f88870db8d7c9255dc5bbd426
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4005
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The Silicon Labs EM3587 and EM3588 may have 512K of flash.
This fix allows for 512K to be specifiied on the command line
when flashing a device.
Change-Id: I18cc4bd0d14e1f2069066734a7396bcccf3de941
Signed-off-by: Byron Kubert <byronk@google.com>
Reviewed-on: http://openocd.zylin.com/3795
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
The need for this due to AICE having 3 interfaces
(EP1 IN-Interrupt, EP2 OUT-Bulk, EP6 IN-Bulk).
Without it, the function will choose first two endpoint as
read_ep/write_ep. This filter will check transfer types
when get endpoint-id. Without this patch, AICE will not
get correct endpoint.
Change-Id: I4da93c7de41cd19e5095b4bfb42078b21f40b678
Signed-off-by: Hellosun Wu <wujiheng.tw@gmail.com>
Reviewed-on: http://openocd.zylin.com/3218
Tested-by: jenkins
Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Make the 'offset' parameter optional, if omitted simply start at the
beginning of the flash bank.
Additionally, check if the argument is out of bounds of the flash bank.
Change-Id: Id1959eee5c395666c35f26342c3c50134dd564e5
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3858
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Default values for .first_bank_size_kb and .has_dual_banks fields
described in stm32lx_parts[] do not fully describe
the real device memory layouts.
Basing on:
STM32L0x1 RM0377
STM32L0x2 RM0376
STM32L0x3 RM0367
STM32Lxxxx RM0038
correct values for memory layouts were selected:
id = 0x447 STM32L0xx (Cat.5) <- dual bank flash
for size 192 or 128 KBytes, single bank for 64 KBytes
id = 0x436 STM32L1xx (Cat.4 / Cat.3 - Medium + /
High Density) <- only one size of the bank,
default values are correct
id = 0x437 STM32L1xx (Cat.5 / Cat.6) <- always dual bank,
but size of the bank can be different
For that reason .part_info field in struct stm32lx_flash_bank
is a dynamic field with fields copied from stm32lx_parts[]
and overwriten to correct values
for specific chips and memory sizes.
Change-Id: If638cb0a9916097bfd4eda77d64feaf1ef2d2147
Signed-off-by: Cezary Gapiński <cezary.gapinski@gmail.com>
Reviewed-on: http://openocd.zylin.com/4074
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Fix "couldn't use loader, falling back to page memory writes" error on
stm32l0 which was caused by the use of cortex-m3 instructions in the
flash loader code. The loader is rewritten using cortex-m0 compatible
instructions
Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Change-Id: If23027b8e09f74e45129e1f8452a04bb994c424e
Reviewed-on: http://openocd.zylin.com/4036
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Tim Newsome
Palmer Dabbelt
Dmitry Ryzhov
Megan Wachs
Paul Fertser
Tobias Diedrich
Grzegorz Kostka
Forest Crossman
Juha Niskanen
Salvador Arroyo
Salvador Arroyo
Matthias Welwarsky
Marc Schink
Byron Kubert
Hellosun Wu
CezaryGapinski
Armin van der Togt