Commit Graph

10821 Commits

Author SHA1 Message Date
Tim Newsome 4f97898889 Merge commit 'd1b882f2c014258be5397067e45848fa5465b78b' into from_upstream
Conflicts:
	doc/openocd.texi
	src/target/riscv/riscv-013.c
	src/target/riscv/riscv.c

Change-Id: I8cd557a10c3d5beeaed05ecc05d4c325a9ee7e70
2023-02-28 10:54:48 -08:00
Tim Newsome b8f4b8887b
Merge pull request #802 from riscv/regression_test
Smoke test OpenOCD against spike.
2023-02-28 09:09:07 -08:00
Tim Newsome 8933785ab3
Merge pull request #801 from Du-Chao/freertos
Set the current_thread when no FreeRTOS task was created.
2023-02-20 08:59:40 -08:00
Tim Newsome 13b0afaf82 Smoke test OpenOCD against spike.
Choosing to grab the latest version of each component. I'd rather deal
with the rare failure that causes, than realize that we've been testing
against really old stuff.

Change-Id: I17321d70e2b54086e8f3fbb01744746633d7a119
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-17 12:50:05 -08:00
Chao Du 1655620c0c Set the current_thread when no FreeRTOS task was created.
The 'current thread' was not set when no FreeRTOS task created. Which could lead a wrongly invoking of freertos_get_thread_reg_list.

Change-Id: I0e0f8327080ef698d7ed4aae5ac2a630d532ddeb
Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-17 07:45:05 +00:00
Tim Newsome 87f9e590b9
Merge pull request #799 from riscv/icount
Add `riscv icount` command.
2023-02-16 10:16:30 -08:00
Anatoly Parshintsev da5d2748e6
target/riscv: hide_csrs configuration option (#787)
* target/riscv: hide_csrs configuration option

This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml

Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a

* Update doc/openocd.texi

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

* Update src/target/riscv/riscv.c

Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>

---------

Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-02-15 09:53:37 -08:00
Jan Matyas 872ebb14ca
Add command "exec_progbuf" (#795)
* Add command "exec_progbuf"

Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.

Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Updated the doc:

- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.

Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

* Cosmetic changes

Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>

---------

Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-15 09:53:03 -08:00
Tim Newsome 9cafc75678
Merge pull request #796 from Du-Chao/freertos_log
Improve a debug log in freertos_update_threads()
2023-02-15 09:52:36 -08:00
Tim Newsome 7c3a77c37a Clarify that RISC-V triggers are optional.
Change-Id: I3a1f5a30385969964351b6ccadf09a3796d34d6b
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-15 09:41:55 -08:00
Tim Newsome fb3376b7f0 Add `riscv icount` command.
Also refactor shared code for clearing itrigger/etrigger/icount.

Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-15 09:31:44 -08:00
Tim Newsome a57fc5e78c
Merge pull request #794 from riscv/fix-fence-instruction
Fix opcode for the "fence" instruction
2023-02-14 10:51:13 -08:00
Tim Newsome 2b4826cd32
Merge pull request #797 from riscv/Zve32
If XLEN=64 and vsew=64 fails, fall back to vsew=32.
2023-02-10 12:36:48 -08:00
Tim Newsome f4f3ce7db7 Don't reuse a single riscv_program.
Because riscv_program_exec() tries to add an instruction every time
through.

This would cause an error accessing vector registers where VL > 14(?).

Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:21 -08:00
Tim Newsome abb918685f If XLEN=64 and vsew=64 fails, fall back to vsew=32.
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.

Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10 11:51:17 -08:00
Tim Newsome 282ac9884e
Merge pull request #798 from aap-sc/aap-sc/mcounteren_fixup
CSR_MCOUNTEREN should not exist if U-mode is not supported
2023-02-10 11:45:54 -08:00
Parshintsev Anatoly 5845f3b71c CSR_MCOUNTEREN should not exist if U-mode is not supported
Change-Id: I1a2420fb88bd3ee37f6a539992e8dc119fdd6e0e
2023-02-10 02:08:40 +03:00
Tim Newsome 344e8bd263 Print out debug value after the assignment is made.
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
2023-02-08 11:02:51 -08:00
Tim Newsome 91552c7999 Move yes_no_maybe_t into riscv.h.
Change-Id: I5bbdc1af3147e05e25612bf496f409111248c979
2023-02-08 11:02:20 -08:00
duchao 9cc6749370 Improve a debug log in freertos_update_threads()
To make the log more accurate and comprehensible. In case the offset is
non-zero.

Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-08 03:01:57 +00:00
Jan Matyas 2c96555c73 Fix opcode for the "fence" instruction
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.

Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).

This patch fixes it by using the proper "fence rw,rw"
instruction.

Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-01 14:59:33 +01:00
Tim Newsome 9c3a4b458c
Merge pull request #786 from aap-sc/aap-sc/vcsr_support
target/riscv: added support for missing VCSR register
2023-01-18 08:53:46 -08:00
Parshintsev Anatoly 71e3d0aecb target/riscv: added support for missing VCSR register
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2023-01-10 17:41:13 +03:00
Tim Newsome 43ea20dfbb
Merge pull request #777 from riscv/itrigger
target/riscv: Add `riscv` `itrigger` and `etrigger` commands.
2023-01-04 10:31:55 -08:00
Tim Newsome 5a72150604
target/riscv: Remove `riscv test_sba_config_reg` command. (#780)
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.

So delete 400 lines of code instead of trying to fix it.

Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:54:33 -08:00
Tim Newsome d2ebfc8770 target/riscv: Use unsigned int for trigger indexes.
Change-Id: I1f7cf3a5c8b86f3d6825f45a67ff05822ea67d28
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:08:18 -08:00
Tim Newsome 9efa7775d4 target/riscv: Read back tdata2 in set_trigger()
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03 10:06:12 -08:00
Tim Newsome 6c027e0df4 target/riscv: Add `riscv etrigger` command.
Change-Id: I7982231c5067b82e4ddb2999bca51dba06ccac7a
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:45 -08:00
Tim Newsome 0b022a349e target/riscv: Add `riscv itrigger` command.
This lets the user set an itrigger trigger, which doesn't fit in the
normal breakpoint abstraction.

This implementation only allows control of a single itrigger. Hardware
could support more than one, and that may be useful to catch different
interrupts in different execution modes. But it would make the code/UI
more complex and it feels like an unlikely use case.

Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02 13:54:35 -08:00
Tim Newsome 2258a59a0f target/riscv: Use macros for trigger types.
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27 12:54:12 -08:00
Tim Newsome eb8bb957d4
flash: fix clang static analyzer build errors (#778)
Fixes "variable set but not used" errors.
Tested with Homebrew clang version 13.0.1

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ia90baf5b4857db2b5569ebe6adbbb832de772aad
Reviewed-on: https://review.openocd.org/c/openocd/+/6971
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Co-authored-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-12-27 10:54:26 -08:00
Dolu1990 b337b0cfb4
riscv/run_algorithm : Add support for memory parameters (#773)
* riscv/run_algorithm : Add support for memory parameters

Change-Id: I5045a3843dcd96edb0cf8cc54bbd41969e3260a6
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : better parameter handeling

Change-Id: If3da8b83f784ef7b13ca83e98bc629e2219cc632
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

* riscv/run_algorithm : Better mem param error reporting

Change-Id: I09f99ca117f7e5373b23cad0f69d9d5b2a77e61d
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>

Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
2022-12-02 09:38:40 -08:00
Tim Newsome f7a5f4719d
Merge pull request #772 from riscv/resume_state
target/riscv: Set target->state in riscv013_halt_go()
2022-11-30 10:21:24 -08:00
Tim Newsome 86e84d3f6d target/riscv: Set target->state in riscv013_halt_go()
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.

Hopefully fixes #749.

Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-29 09:24:24 -08:00
Tim Newsome d6bf022560
Merge pull request #767 from riscv/unavailable
Handle harts becoming unavailable while they're being debugged.
2022-11-25 10:18:12 -08:00
Tim Newsome 2d7dc3f5f5 target/riscv: Fix small riscv013_halt_go() bug
Exit the loop when no harts are running, instead of when at least one
hart has halted.

Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome 69222be761 target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK
Simple rename to make code slightly more clear.

Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 13:00:01 -08:00
Tim Newsome bf15b00315 target/riscv: Set correct target->state in riscv013_halt_go()
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.

Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23 12:59:58 -08:00
Tim Newsome e69735db0b gdb_server: Operate on available targets.
When SMP is enabled, gdb will always use the first target in the SMP
group. That doesn't work when that first target is unavailable, but
others in the SMP group are still available.

For cases where gdb expects an operation to affect the entire group (run
control, memory access), find the first available target in an SMP group
and use that.

Change-Id: I4bed600da3ac0fdfe4287d8fdd090a58452db501
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome b1f3a75819 target/riscv: Don't resume unavailable harts.
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome d3bffe3d86 target/riscv: Share single-target and SMP resume code.
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome 5832b983f5 rtos/hwthread: Hide unavailable targets from thread list.
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:50 -08:00
Tim Newsome ad93fda7e8 target/riscv: Make poll() use TARGET_UNAVAILABLE.
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22 09:29:47 -08:00
Tim Newsome e5f9024bb0 target/riscv: Refactor riscv_openocd_poll()
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.

Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome 5a48975118 target/riscv: Error when hart becomes unavailable during resume
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21 10:26:21 -08:00
Tim Newsome cc5e78172a
Merge pull request #769 from riscv/0.11
Revive 0.11 debug spec support
2022-11-21 09:26:38 -08:00
Tim Newsome f1e20767bc target/riscv: 0.11, call handle_halt() after step
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.

Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 11:41:27 -08:00
Tim Newsome e16d7a5611 target/riscv: Ignore maskmax when reading back tdata1
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.

Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17 11:41:24 -08:00
Tim Newsome bec0fe2236
target/riscv: Don't always read on DMI batch write (#768)
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.

riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG  scan
operation.

When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.

This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.

Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling  to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.

This doubles download speeds to spike using remote bitbang.

Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>

Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17 11:34:27 -08:00
Tim Newsome fc210e8689 target/riscv: Ignore debug_execution in 0.11 resume
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)

Fixes #757.

Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17 09:49:28 -08:00