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Clarify that RISC-V triggers are optional. 

Change-Id: I3a1f5a30385969964351b6ccadf09a3796d34d6b
Signed-off-by: Tim Newsome <tim@sifive.com>
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Tim Newsome 2023-02-15 09:37:29 -08:00
parent fb3376b7f0
commit 7c3a77c37a
1 changed files with 3 additions and 2 deletions
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doc/openocd.texi
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@ -10718,8 +10718,9 @@ Perform a 32-bit DMI write of value at address.
@subsection RISC-V Trigger Commands
The RISC-V Debug Specification defines several trigger types that don't map
cleanly onto OpenOCD's notion of hardware breakpoints. These commands let you
The RISC-V Debug Specification defines several optional trigger types that don't
map cleanly onto OpenOCD's notion of hardware breakpoints. For the types that
the target supports, these commands let you
set those triggers directly. (It's also possible to do so by writing the
appropriate CSRs.)