From 7c3a77c37aebfe52b3e18e4f568399590debbe4a Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 15 Feb 2023 09:37:29 -0800 Subject: [PATCH] Clarify that RISC-V triggers are optional. Change-Id: I3a1f5a30385969964351b6ccadf09a3796d34d6b Signed-off-by: Tim Newsome --- doc/openocd.texi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/openocd.texi b/doc/openocd.texi index 27543d9e6..d1aba3601 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -10718,8 +10718,9 @@ Perform a 32-bit DMI write of value at address. @subsection RISC-V Trigger Commands -The RISC-V Debug Specification defines several trigger types that don't map -cleanly onto OpenOCD's notion of hardware breakpoints. These commands let you +The RISC-V Debug Specification defines several optional trigger types that don't +map cleanly onto OpenOCD's notion of hardware breakpoints. For the types that +the target supports, these commands let you set those triggers directly. (It's also possible to do so by writing the appropriate CSRs.)