Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.
Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
* WIP, apply stash with conflicts.
Change-Id: Ia794bde419aa29161c68898d20e30527e69f5a31
* Fix conflict resolution problems.
Change-Id: I4cedc348cf613f98cc5a36886f37c568ca644238
* Add repeat_read command.
Only implemented for sba v1 right now, and poorly tested at that.
Change-Id: I1d9ff63e1dea14b3f6a9f8ba4dad53668bf8038b
* Hide bogus address in repeat_read
Change-Id: Ib66c1fa60df9c7fc7cc87880b0fddc52825b48aa
* WIP make repeat read work with progbuf.
Change-Id: I555f8b880c8bf0d1ed0f3f90c7987a5b516a7a79
* WIP
Change-Id: Ic567cea68355ae907e94bd25185a2c9be6fd798d
* Fix error handling when increment is non-zero.
Change-Id: I5a2f3f2ee948fd4e12c0443a542e85b7b5c5791a
* Correctly(?) handle failures when increment is 0.
I'm not 100% convinced that this ensures every read value shows up in
the output, but it ought to work.
Change-Id: I1af3e7174cf9d5e6f293456fb5ead629e17faaaa
* Don't crash when asked to read no data.
Change-Id: I4061b5c720a43a4f828384ab9eacc89557adfa05
* Remove unnecessary comment.
Change-Id: I1be3d699b86299339b3a830ca1ef13c9f5b9fe0f
* Document `riscv repeat_read`.
Change-Id: I4a0f071f38784b2de034f8c1b0ce75d6d2d326b2
* WIP making semihosting work with -rtos hwthread.
Change-Id: Icb46f3eeedc1391e8fdc73c3ad8036f20267eb2e
* More WIP.
Change-Id: I670a6e1ba2a13a6ef2ae303a99559a16fdd1bbfb
* Fix halting due to a trigger.
Change-Id: Ie7caa8dde9518bcd5440e34cf31ed0d30ebf29ad
* Fix multicore semihosting without halt groups.
Change-Id: I53587e5234308ed2cc30a7132c86e4c94eb176c4
* WIP
Change-Id: I40630543b08d8b533726cb3f63aa60a62be8ef40
* Fix single core semihosting.
This was the last bug!
Change-Id: I593abac027fa9707f48b7f58163d7089574a0e28
* Fix whitespace.
Change-Id: I285c152970b87864c63803fae61312e5b79dfe6d
Line continuation, adding a backslash as last char of the line, is
requested in multi-line macro definition, but is not necessary in
the rest of C code.
Remove it where present.
Identified by checkpatch script from Linux kernel v5.1 using the
command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types LINE_CONTINUATIONS -f {} \;
Change-Id: Id0c69e93456731717a7b290b16580e9f8ae741bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5619
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.
The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:
find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
--types UNNECESSARY_BREAK -f {} \; \
| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
| awk 'function P() {print "sed -i '\''"b"'\'' "a};
{
if ($1!=a) {
if (a) {P()};
a=$1;
b=$2"{d}";
} else {
b=b";"$2"{d}"
}
};
END {P()}'
Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
BUILD_TARGET64 creates a larger test matrix and mostly gates the
building of the aarch64/armv8 target, make that unconditional, which
would help fixing any issues with 64-bit address types anyway.
Rebased by Antonio Borneo after commit 1fbe8450a9 ("mips: Add
MIPS64 support")
Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
Suggested-by: Matthias Welwarsky <matthias@welwarsky.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5240
Tested-by: jenkins
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)
Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types POINTER_LOCATION --fix-inplace -f {} \;
then manually reviewed.
OpenOCD coding style does not mention the space around pointer's
asterisk, so no check is enforced. This patch only makes the style
uniform across the files.
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Iefb4998e69bebdfe0d1ae65cadfc8d2c4f166d13
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5197
Tested-by: jenkins
* WIP
Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd
* Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right.
Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
* Total hack to communicate registers to gdb.
Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765
* Implement writing vector registers.
Fixed reading vector registers.
Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214
* Show gdb the actual size of the vector registers.
This length may be different per hart.
Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493
* Remove outdated todo comment.
Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128
* Removed TODO comment.
Filed #449 to track this.
Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47
* Nicely handle some errors reading/writing V regs.
Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
* Handle DMI busy in sba write.
If we encounter DMI busy on the NOP after a read, we'll never get the
value out because DMI busy is sticky. The read must be retried, but we
don't know whether it was ever issued. Since the read has side effects
(incrementing of the address) this retry must be handled at a higher
layer. So now dmi_op_timeout can be told to retry or not, and if retry
is disabled it'll return an error when busy.
Also actually properly do the retry in dmi_op_timeout(). Previously the
code would not reissue the command and end up returning a garbage value.
Change-Id: I3b52ebd51ebbbedd6e425676ac861b57fbe711b1
* Fix whitespace.
Change-Id: Icb76d964e681b22346368d224d1930c9342343f3
* Handle a few more DMI busy cases.
Change-Id: I8503a44e4bf935c0ebfff0d598fe4c322fda702a
* Explain when to use dmi_op_timeout(retry).
Change-Id: I1a5c6d76ac41a84472a8f79faecb2f48105191ff
* dmi_reset does not affect the current transaction.
That means the retry scheme we had been using works fine. This does
contain some minor tweaks, and now we pass my tests which hammer the DMI
busy case harder.
Change-Id: I13eee384dbba82bc5a5b1d387c75c547afe557b5
* Remove unnecessary changes to make the PR readable
Change-Id: I87079876e6965563cf590e3936b3595aeab8715d
* Move idle to end of line...
... because we go through run-test/idle after the scan.
Change-Id: I21a8cff22471f0b895d8cd8d25373dced9bf1ca9
* Remove unused code.
Change-Id: I07a7cdd2d64ca40a4fe181111a34cf55ff1928d1
The original OpenOCD code issued FENCE & FENCE.i twice for the current
hart (which is harmless, but takes time).
Avoiding this extra FENCE is a slight performance improvement. Per my rough
measurements, this improves performance of certain debugger actions
(single-stepping) by approx. 20% in single-hart systems.
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
Fix memory access on 64-bit targets with no progbuf and sba that
supports 32-bit accesses but not 64-bit accesses. Bug was introduced in #419.
This fixes https://github.com/riscv/riscv-tests/issues/217.
Change-Id: Ib5ddf9886b77e3d58fe1d891b560ad03d5a46da1
When allocating scratch memory within RISC-V target
(scratch_reserve()), take into account whether progbuf
is writable or not, as determined by examine_progbuf().
* fix for batch scans not honoring presence of BSCAN tunnel
* fix formatting to placate checkpatch
* replace DIM with ARRAY_SIZE
* Refactor code that adds a bscan tunneled scan.
* Move bscan tunnel context to the batch structure, and in array
form, one per scan
* adjust code that was inconsistent with project code formatting standards
* 64-bit progbuf memory reads work.
Change-Id: Ia3dbc0ee39a31ed0e5c38bbb3d9e089b2533f399
* 64-bit writes work.
Change-Id: Iae78711d715b6682817bb7cce366b0094bda8b23
* Let targets indicate number of supported data bits.
This is used by the default memory read/write functions when creating an
aligned block.
I'm adding this mainly to ensure I get coverage of the 64-bit progbuf
memory read/write code.
Change-Id: Ie5909fe537c9ec3360a8d2837f84be00a63de77b
* Make mingw32 happy.
Change-Id: Iade8c1fdfc72ccafc82f2f34923577032b668916
* Add riscv_batch_available_scans().
This function will query the number of available scans in a batch.
* Perform SBA writes with batch transactions for improved performance.
Using batch transactions avoids an unnecessary dmi read after every
dmi write, resulting in a significant performance improvement.
* Align algorithm stack to XLEN.
This fixes algorithm timeout on RV64 targets.
Also improve debug information in various places.
Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d
* Compile 32-bit RISC-V algorithms for RV32E.
Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa
* Remove debug code.
Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b
* Dump start of gdb packets escaping non-printable.
Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915
* Propagate flash programming errors.
Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7
* Improve debug messaging.
Change-Id: I47ac3518f3b241986c677824864102936100adf6
* Add debug output to flash image.
This is helpful when you're debugging the flash algorithm itself, and a
nop when running it through OpenOCD.
Change-Id: Id44c6498c288872cc2cec79044116ac38198c572
* Make timeout depend on how much data is written.
Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e
* Fix issi erase commands.
This is required to flash HiFive Unleashed.
Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10
* Fix running algorithm on multicore `-rtos riscv`.
The bug was that poll() might change the currently selected hart, and in
that case we'd access registers on that other hart after the algorithm
is finished.
Change-Id: I140431898285cf471b372139cef2378ab4879377
* Make fespi flash algorithm debugging optional.
Also add a scheme that allows you to see the stack trace of where a
failure occurred if debugging is enabled.
Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
* Clear cmderr by writing all ones.
This should have been part of #389.
Change-Id: Ie40e95fdd904af65c53d1f5de7c8464b27038ec0
* Don't update reg cache in register_write_direct().
This function explicitly bypasses any caches.
Change-Id: Ie3c9a1163e870f80c0ed75b74495079c527663e9
* Use only one hart to run algorithm.
Fixes a bug with `-rtos hwthread` where all harts would run when running
a flash/CRC algorithm, which would probably ruin flashing, and was
unexpectedly changing registers on other harts for the CRC algorithm.
Change-Id: Ia2f600624f4c8d4cab319861fef2c14722f08b53
* Adds support for RISCV Access Memory Abstract Commands
The Access Memory Abstract Command is one of the three optional
methods for reading and writing memory on a complient RISCV
debug module. The previous two options were already implemented
in OpenOCD.
Implementation Notes:
- aamvirtual is hard-coded to false until the design for accessing
virtual addresses is finalized.
- aamsizes corresponding to 8b, 16b, 32b, and 64b are supported.
128b support is postponed until it is required, as it will mean
changes to the read/write_abstract_arg() interface to pass 128b
values.
- aampostincrement is not used and hard-coded to false.
* Changes from review.
* Additional lint fixes and a typo from last commit.
* Fixing a clang error.
* Fixes a last-minute change that broke writes with width > 8b.
* Removing memcpy after adding read_from_buf().
* add opcode for csrrsi and csrrci
* enable MMU while reading/writing memory using progbuf
* fix style issues
* keep old behavior for progbufsize<4, perform r/w/csr only when necessary
* do not pass progbufsize, only write mstatus if changed
* add config option to enable virtualization feature
* throw error if virt enabled but unavaliable, outsource modify_privilege
* support virtualization for read_memory_progbuf_one
gdb has developed a nasty habit of very often reading 30-some
half-words. This change speeds that up significantly.
Change-Id: Iab1b7575bec5c57051c6e630ae292dddf8fe6350
* Cache program buffer writes.
Speeds up flash program by 3%, flash verify by 2%.
Change-Id: I19f8f44f560a1111fa8f4e4fc04ce6de3c94999a
* Remove nop from batch reads.
program @ 22.123 KiB/s, verify @ 47.654 KiB/s (up from program @ 20.287
KiB/s, verify @ 23.148 KiB/s originally).
Change-Id: I7ee19d967b1080336b0088d20e1fc30828afd935
* Use "algorithm" to compute CRC on RISC-V targets.
Use the C compiler to generate the algorithm code. It's better at
assembly than I am. We need separate RV32 and RV64 binaries to handle
shift instructions. I used the code from gdb (libiberty really) because
it returns the correct result. I'm not sure if the table is worth it
since we do have to save/download/restore more bytes now.
riscv_run_algorithm() now properly saves and reads back all registers
used for parameters. It also doesn't check final_pc if exit_point is 0.
Using gdb means I don't know the exact address where the code will end.
Small target.[ch] change to be able to run algorithms at 64-bit
addresses.
Flashing an arty board now:
```
wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 105.589180s (20.608 KiB/s)
verified 2192012 bytes in 7.037476s (304.177 KiB/s)
9.87user 16.16system 1:53.16elapsed 23%CPU (0avgtext+0avgdata 24768maxresident)k
```
Change-Id: I6696bd4cda7c89ac5ccd21b2ff3aa1663d7d7190
* Clean up formatting.
Change-Id: I7f2d792a2b9432a04209272abb00d8136ee01025
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode
Given the variable supported message length , a prefix decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len = max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected.
* style patch
* non-conflict with original
* style patch
* style patch
* requested changes
* style-patch
* Fix small SBA bug.
We were not compliant with the spec, but I'm not sure if this was
causing problems for anybody.
Change-Id: Ia31ee400fd75ad907349c4dd995b1e03bd2116c7
* Don't write sbcs while sbbusy is set.
Probably not hurting anything, but the spec says we shouldn't.
Also propagate more errors, and fully decode sbcs in debug output.
Change-Id: I1a36646772fe794c8780702565103a309bbcc5e9
Currently the RISC-V compliance test suite doesn't output the test is
currently runs before it succeeds. It also uses the same message for
many tests. This makes it very hard to find out which test fails.
This commit makes things slightly easier by printing the test that's
being executed before it actually runs, and by adding the source code
line where the test is located, making it easier to look up the test in
the source code.
New output looks like this:
Info : Executing test 149 (riscv-013.c:3800): Regular calls must return ERROR_OK
Info : PASSED
The test assumes that the target has been examined. If that fails (for
whatever reason) the test will segfault:
Program received signal SIGSEGV, Segmentation fault.
register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
109 struct reg *reg = cache->reg_list;
(gdb) bt
0 register_cache_invalidate (cache=0x0) at ../src/target/register.c:109
1 0x0000000000520735 in riscv_invalidate_register_cache (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2160
2 0x000000000052224f in riscv_halt_all_harts (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2022
3 0x0000000000574e82 in riscv013_test_compliance (target=0x779b50) at ../src/target/riscv/riscv-013.c:3600
* Remove unnecessary 0.11 code.
Don't need need_strict_step anymore now that we have
riscv_hit_watchpoint().
Don't need 32-bit warning in riscv011_resume() now that address is a
target_address_t.
Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc
* WIP little refactor working towards hasel support.
Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf
* More refactoring.
Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b
* More refactoring.
Change-Id: Icea1308499492da51354f89e1529353e8385f3a1
* Starting to work towards actual hasel changes.
Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e
* Implement simultaneous resume using hasel.
Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f
* Add support back for targets that don't have hasel.
Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a
* Make hasel work with >32 harts.
Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`
Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
If the hardware supports it, when one hart in an SMP group halts all the
other harts in that same SMP group will automatically, quickly, halt as
well.
Change-Id: Ida81f1309c180674e8c9d8060e3d2a4bbb910a6f
* Implement riscv_get_thread_reg().
This is necessary because riscv_get_gdb_reg_list() now reads all
registers, which ended up causing `-rtos riscv` to read all registers
whenever one was requested (because the register cache is wiped every
time we switch to a different hart).
CustomRegisterTest went from 1329s to 106s.
Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32
* Also implement riscv_set_reg().
Now all the `-rtos riscv` tests pass again, at regular speed.
Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1
* Better error messages.
Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5
* Add target_get_gdb_reg_list_noread().
Being explicit about what's expected gets `-rtos riscv` back to `-rtos
hwthread` time.
Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7
* Revert a change I made that has no effect.
I don't understand exactly what all this test protects against, and I
shouldn't change it unless I do.
Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
Rename dtmcontrol_idle to dtmcs_idle, because the register is now called
dtmcs.
Simplify read_memory_progbuf_inner(), getting rid of several unnecessary
variables.
Change-Id: Ibac655a45c63cf2210ab282568b54f8097526c10
* Install patchutils for the build.
This contains filterdiff, which we need to check that our changes
conform to OpenOCD style.
Change-Id: Id522f4e62fee3efad4e0e00933abfeada9635624
* Fix paths for filterdiff line.
Change-Id: Ic50e13c7fe64e65b2d2af0260fb19c07a9f10e20
* Conform to OpenOCD style.
Change-Id: I51660d30404c0a625b58c9bed2d948695575e72e
* Changed logging level
* Added logging statement
* Removed halt event when attaching to target
* Extended some packet handling
* Extended handling of rtos_hart_id and clearing of register cache
* Extended execute_fence to handle all harts
* Removing logging statement again
* Updated according to review comments
* Forgot to re-add the return statement
* Was removing too much for the if statement to work
* This needs to >= 3 now to handle both a fence and a fence.i
* Added `riscv expose_custom` command.
Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.
Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f
* Conform to OpenOCD style.
Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf
* Free all the memory allocated by register init.
Change-Id: I04e35ab54613f99708cee85e41fef989079adefc
* Properly document `riscv expose_custom`.
Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
This supports both 0.11 and 0.13 versions of the debug spec.
Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.
Flash support for the SiFive boards will also come in a later commit.
Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The main difference is we need to deal with hartsello/hartselhi. (Note
that there's a compile-time limit to 16 harts, but that can be changed.)
My largest target has 4 harts, so I can't tell how well this really
works. But it doesn't break anything.
Fixes#240.
Change-Id: Ie1a2a789b5e00f55174994568749da1cf3a33b92
This improves startup time, which is important when connecting to
simulators. One problem is that triggers that are set when the debugger
connects are not cleared until enumeration happens. Execution may halt
due to a trigger set by a previous debug session, which could confuse
the user. If this happens, triggers will be instantly enumerated, so it
will only happen once per session.
Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
* Enforce OpenOCD style guide.
Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8
* Fail if `git diff` fails
Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9
* Maybe every line gets its own shell?
Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6
* Maybe this will error properly.
Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9
* Take different approach than merge-base
Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1
* Fix style issues.
Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
This saves us from re-reading s0 before doing just about anything
program buffer related.
Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.
Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
Tim Newsome
Samuel Obuch
Jan Matyas
Antonio Borneo
Florian Fainelli
Tomas Vanek
Greg Savin
darius-bluespec
dave-estes-syzexion
Nils Wistoff
Paul George
Philipp Wagner
Carsten Gosvig
cgsfv
Ryan Macdonald
Megan Wachs