Icount triggers don't have a maskmax field at all. This is a cut and
paste error.
Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
Untested, because I don't have a target that implements this.
Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
It is possible for triggers of the same type to support different match
field values, so it is needed to try all the triggers, not just the
first one.
Fixes issue #788.
Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com
Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]
Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
* target/riscv: hide_csrs configuration option
This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml
Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a
* Update doc/openocd.texi
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
---------
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* Add command "exec_progbuf"
Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.
Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Updated the doc:
- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.
Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Cosmetic changes
Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
---------
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
Also refactor shared code for clearing itrigger/etrigger/icount.
Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255
Signed-off-by: Tim Newsome <tim@sifive.com>
Because riscv_program_exec() tries to add an instruction every time
through.
This would cause an error accessing vector registers where VL > 14(?).
Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.
Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.
Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).
This patch fixes it by using the proper "fence rw,rw"
instruction.
Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.
So delete 400 lines of code instead of trying to fix it.
Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
This lets the user set an itrigger trigger, which doesn't fit in the
normal breakpoint abstraction.
This implementation only allows control of a single itrigger. Hardware
could support more than one, and that may be useful to catch different
interrupts in different execution modes. But it would make the code/UI
more complex and it feels like an unlikely use case.
Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91
Signed-off-by: Tim Newsome <tim@sifive.com>
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.
Hopefully fixes#749.
Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
Exit the loop when no harts are running, instead of when at least one
hart has halted.
Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.
Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.
Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.
Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.
Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.
riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG scan
operation.
When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.
This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.
Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.
This doubles download speeds to spike using remote bitbang.
Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)
Fixes#757.
Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
Tim Newsome
Mark Zhuang
Evgeniy Naydanov
Hang Xu
Anatoly Parshintsev
Jan Matyas
Parshintsev Anatoly
Jan Matyas
Dolu1990