Commit Graph

547 Commits

Author SHA1 Message Date
Farid Khaydari 173086a651 target/riscv: early exit support for memory access operations
(1) Error code and 'skip_reason' string were replaced with memory access
    status. It allows to specify whether OpenOCD should exit the access
    early.
(2) Slightly refactored 'read_memory' and 'write_memory' functions.

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-09-27 12:27:11 +03:00
Tim Newsome 77bffed1c4 target/riscv: Fix calloc calls.
This was pointed out by gcc. Presumably it's a newer warning. I doubt it
has any effect on anything.
2024-09-06 08:34:58 -07:00
Evgeniy Naydanov d58c656f72
Merge pull request #1111 from en-sc/en-sc/ref-reg-manual-hwbp
target/riscv: manage triggers available to OpenOCD for internal use
2024-09-06 15:57:38 +03:00
Evgeniy Naydanov d7a7c9822e
Merge pull request #1125 from fk-sc/fk-sc/field-duplication
target/riscv: remove duplicate of progbufsize field
2024-09-06 12:23:37 +03:00
Evgeniy Naydanov 5a8697b3cf target/riscv: manage triggers available to OpenOCD for internal use
Before the change, if the user wrote to any `tdata*` register, OpenOCD
would sometimes start to disable all the triggers (by writing zeroes to
`tdata1`) and re-enable them again (by witing all trigger registers to the
values read before for each `tselect` value), e.g. on `step`
(see `disable/enable_triggers()`).

There are a couple of issues with such approach:
1. RISC-V Debug Specification does not require custom register types
   to support re-enabling by such sequence of writes (e.g. some custom
   trigger type may require writing a custom CSR to enable it).
2. OpenOCD may still overwrite these triggers when a user asks to set a
   new WP.

This commit introduces `riscv reserve_trigger ...` command to explicitly
mark the triggers OpenOCD should not touch.

Such approach allows to separate management of custom triggers and
offload it onto the user (e.g. disable/enable such triggers by setting up
an event handler on `step`-related events).

Change-Id: I3339000445185ab221368442a070f412bf44bfab
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-09-05 12:59:35 +03:00
Evgeniy Naydanov 909bbb899b
Merge pull request #1115 from en-sc/en-sc/fixup-bscan
target/riscv: restrict BSCAN-related commands to before-`init`
2024-09-04 19:40:41 +03:00
Farid Khaydari a61e7271ef target/riscv: remove duplicate progbufsize field
* removed `progbuf_size`  field from `riscv_info`; added getter
* moved `impebreak` field from `riscv_info` to `riscv013_info`
  as implementation dependent field; added getter

Signed-off-by: Farid Khaydari <f.khaydari@syntacore.com>
2024-09-04 17:55:14 +03:00
Evgeniy Naydanov 342f294031 target/riscv: restrict BSCAN-related commands to before-`init`
Logically, BSCAN tunneling is used to establish a connection, therefore
it should be set up before the communication starts (i.e. before
`init`).

Moreover, current implementation does not support changing
`bscan_tunnel_ir_width` after `init`. This is evident by RISC-V handler
of the `init` itself.
Link: 9a23c9e679/src/target/riscv/riscv.c (L467-L481)

Change-Id: I817c6a996f7f7171b2286e181daf1092bd358f69
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-08-14 20:50:32 +03:00
Evgeniy Naydanov 4379e84380 target/riscv: remove duplicate `dtmcontrol_scan()`
Also avoid receiving data if the value is discarded on the call-site.

Change-Id: Ied87b551536a00d9fad469b9843cccae1976e6b6
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-08-14 20:13:36 +03:00
Evgeniy Naydanov 9a489be795 target/riscv: single DMI accesses via batch
* Eliminates the use of VLA, which is prohibited by `doc/manual
/style.txt`:
Link: c6bb902629/doc/manual/style.txt (L164-L166)

* Unifies DMI access interface.

* Reduces code duplication.

Change-Id: I2d7b0595f171e21062049ff61f76fb5a3c992d11
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-16 16:43:46 +03:00
Evgeniy Naydanov f3abfe49fd target/riscv: deprecate `riscv set_reset_timeout_sec`
Change-Id: I46bf3e4dab2a99c97b7ab133a85c13332365f9b7
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-04 12:20:38 +03:00
Evgeniy Naydanov 3883b03aaa target/riscv: separate register cache stuff into files
This commit creates file structure for register cache related
functions.
Specifically:

* `riscv_reg.h` -- general interface to registers. Safe to use after
  register cache initialization is successful.
* `riscv_reg_impl.h` -- helper functions to use while implementing
  register cache initialization.
* `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and
  `riscv_reg_impl.h`.
* `riscv-011_reg.h` -- register cache interface specific to 0.11
  targets.
* `riscv-013_reg.h` -- register cache interface specific to 0.13+
  targets.
* `riscv-011/0.13.h` -- version-specific methods used to access
  registers. Will be extended as needed once other functionality (not
  related to register access) is separated (e.g. DM/DTM specific stuff).

Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-02 10:15:20 +03:00
Evgeniy Naydanov cb87885c00 target/riscv: stop using register_get/set for 0.11 targets
Caching is somewhat handled in `riscv-011.c`. Handling it additionaly in
`riscv.c` may cause problems. Sice there is no simulator that supports
RISC-V Debug Specification v0.11, so it is not feaseable to automate
testing.
This commit separates 0.11 register accesses and unlocks further
development in this area.

Change-Id: I73ff17ef85106c4ababa38319f446f6c384a1750
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-06-04 19:22:11 +03:00
Anatoly Parshintsev b548653f66
Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_status
target/riscv: fix halt reason for targets that do not support hit bit on triggers
2024-06-04 18:49:42 +03:00
Parshintsev Anatoly b201a5db23 target/riscv: do not emit warnings when a non-existent CSR is hidden
hide_csrs should not emit warnings on an attempt to hide non-exitents CSR.
hide_csrs funcitonality is intended to be used for scenarios when we don`t
want certain groups of registers to be available in GDB. Typically this is
needed to simplify integration with various IDE. In such scenarious it may
be impractical/unfeseable to figure out which register is present on a
target. So reporting a situation when a user wants to hide a non-existent
register creates way too much noise. This commit reduces severity of
relevant debug message to LOG_TARGET_DEBUG
2024-05-28 22:45:37 +03:00
Parshintsev Anatoly 2c00a087da target/riscv: fix halt reason for targets that do not support hit bit on triggers
Before this patch the following behavior is observed on targets that do
not support hit bit:

```
bp 0x80000004 4 hw
resume 0x80000000
riscv.cpu halted due to watchpoint
```

This happens because the current implementation relies on the presence
of hit bit way too much. While working on this patch few defects in
hit bit-based trigger detection were discovered, added appropriate
TODOs.
2024-05-28 21:46:19 +03:00
Evgeniy Naydanov 4924f63926
Merge pull request #1029 from MrAlexei/add_decode_wp_rvc
Add functions to decode RVC load and store instructions for watchpoints
2024-05-17 16:39:12 +03:00
Evgeniy Naydanov 6a72b323da
Merge pull request #1028 from en-sc/en-sc/busy-reset-batch
target/riscv: reset delays during batch scans
2024-05-02 10:55:16 +03:00
Aleksey Lotosh 69cf9babfb Add functions to decode RVC load and store instructions
For GDB to fully support hardware watchpoints, OpenOCD needs to tell GDB
which data address has been hit. OpenOCD relies on a target-specific
hit_watchpoint function to do this. If GDB is not given the address, it
will not print the hit variable name or its old and new value.

There does not seem to be a way for the hardware to tell us which
trigger
was hit (0.13 introduced the 'hit bit' but this is optional).
Alternatively,
we can decode the instruction at dpc and find out which memory address
it accesses.

This commit adds support for RVC (compressed) load and store
instructions.

Related to:
https://github.com/riscv-collab/riscv-openocd/issues/688
https://github.com/riscv-collab/riscv-openocd/pull/291
2024-04-30 10:50:51 +03:00
Evgeniy Naydanov 687f00c060
Merge pull request #1031 from aap-sc/aap-sc/hart_status_info_fixup
fix confusing status messages during resume
2024-04-27 16:44:09 +03:00
Evgeniy Naydanov 9563cd67e6
Merge pull request #1055 from aap-sc/aap-sc/bp_unitialized
target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/wp descriptor
2024-04-27 16:42:29 +03:00
Evgeniy Naydanov 68fcd1c5b7 target/riscv: reset delays during batch scans
This commit is related to testing how OpenOCD responds to `dmi.busy`.

Consider testing on Spike (e.g. `riscv-tests/debug` testsuite). Spike
returns `dmi.busy` if there were less then a given number of RTI cycles
(`required_rti_cycles`) between DR_UPDATE and DR_CAPTURE:
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L145
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/jtag_dtm.cc#L202
`required_rti_cycles` gets it's value from `--dmi-rti` CLI argument and
is constant throughout the run.

OpenOCD learns this required number of RTI cycles by starting with zero
and increasing it if `dmi.busy` is encountered. So the required number
of RTI cycles is learned during the first DMI access in the `examine()`.

To induce `dmi.busy` on demand `riscv reset_delays <x>` command is
provided. This command initializes `riscv_info::reset_delays_wait`
counter to the provided `<x>` value. The counter is decreased before a
DMI access and when it reaches zero the learned value of RTI cycles
required is reset, so the DMI access results in `dmi.busy`.

Now consider running a batch of accesses.  Before the change all the
accesses in the batch had the same number of RIT cycles in between them.
So either:
* Number of accesses in the batch was greater then the value of
  `riscv_info::reset_delays_wait` counter and there was no `dmi.busy`
throughout the batch.
* Number of accesses in the batch was less or equal then the value of
  `riscv_info::reset_delays_wait` counter and the first access of the
batch resulted in `dmi.busy`.

Therefore it was impossible to encounter `dmi.busy` on any scan of the
batch except the first one.

Change-Id: Ib0714ecaf7d2e11878140d16d9aa6152ff20f1e9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-04-26 21:24:54 +03:00
Parshintsev Anatoly 665fbf605b fix confusing status messages during resume
Recently, (after b503fdef02) OpenOCD started to notify user about hart
state updates. This causes confusion in some cases since some internal
updates to the hart state should not be visible to the user as these are
implementation details. For example situation like this:

```
> reset halt
JTAG tap: riscv.tap tap/device found: 0xdeadbeef ...
> resume
[riscv.cpu0] Found 4 triggers
riscv.cpu0 halted due to single-step.
[riscv.cpu1] Found 4 triggers
riscv.cpu1 halted due to single-step.
[riscv.cpu2] Found 4 triggers
riscv.cpu2 halted due to single-step.
[riscv.cpu3] Found 4 triggers
riscv.cpu3 halted due to single-step.
```
likely confuse people.

There is no issue with the resume functionality. It`s just that
resume internally causes single-step that causes hart state
to change.

This commit disable calling of user-specified (and default)
callbacks during the "hidden" step operation disabling these
confusing messages

Change-Id: I3412a089e2abdcd315d86cec7ee732fdd18c1601
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2024-04-24 02:34:48 +03:00
Parshintsev Anatoly 88f7650a6d target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/wp descriptor
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2024-04-24 02:07:16 +03:00
Evgeniy Naydanov e1e6cdfec6 target/riscv: decode DMI scans in batch access
This allows to merge the implementation in `batch.c` with the one in
`riscv-013.c`.

Change-Id: Ic3821a9ce2d75a7c6e618074679595ddefb14cfc
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-04-19 13:21:19 +03:00
Evgeniy Naydanov 9c45c9f4be target/riscv: read registers are not valid on a running target
Change-Id: I2c5335bb6055b767d3c3ffb3f6910b71b9c2bb35
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-04-05 14:19:33 +03:00
Evgeniy Naydanov ea7e17491d [NFC] target/riscv: refactor `init_registers()`
The logic in `init_registers()` was quite convoluted.
Initialization of each `struct reg` field is separated into function
`gdb_regno_<field_name>()`.
IMHO, this makes it much easier to reason about the code.

Change-Id: Id7faa1464ce026cc5025585d0a6a95a01fb39cee
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-03-21 18:45:14 +03:00
Evgeniy Naydanov 19acf51c39 Merge up to 07141132a7 from upstream
Change-Id: Ibca0c8093e2983e1ee199f79ed777f5136794195
2024-03-07 12:38:57 +03:00
Evgeniy Naydanov ca7d882526
Merge pull request #977 from kr-sc/kr-sc/improve-riscv-controls
target/riscv: Improve riscv controls that manage the set of available triggers for watchpoints
2024-02-27 14:04:49 +03:00
Sevan Janiyan 33573cda4a src/target/riscv: Help older compilers
find members of a union, nested in struct.
Allows file to be compiled with GCC 4.0

Signed-off-by: Sevan Janiyan <venture37@geeklan.co.uk>
Change-Id: Ied68668d3b5f811573a20e11e83aceff268963eb
Reviewed-on: https://review.openocd.org/c/openocd/+/8120
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-02-24 13:37:49 +00:00
Evgeniy Naydanov 9f4c0ba1cc
Merge pull request #1014 from riscv-collab/riscv-batch-cleanup
Fixes and cleanup in riscv batch and related functions
2024-02-21 14:40:48 +03:00
Kirill Radkin 5003b3642c target/riscv: Improve riscv controls that manage the set of available triggers for watchpoints
Add more debug messages connected with triggers.
Update names for internal flags to make them more clarified.

Change-Id: I5642346ce4a1e9bf79b22cdbf36bd757a7beffa8
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
2024-02-13 16:27:12 +03:00
Jan Matyas 5d4fa0001e
Merge pull request #1011 from en-sc/en-sc/wa-halt-groups
target/riscv: set `state` and `debug_reason` in `riscv_halt_go_all_harts()`
2024-02-12 07:51:22 +01:00
Jan Matyas 4f17df0d1d
Merge pull request #1008 from en-sc/en-sc/from_upstream
Merge up to 9659a9b5e2 from upstream
2024-02-09 07:02:29 +01:00
Jan Matyas 67a3d4fe7f Fixes and cleanup in riscv batch and related functions
Fixes:

- Data types of address & data parameters in riscv_batch_add_*()
  and riscv*_fill_dm*() changed to uint64_t and uint32_t.

- Corrected the comparison in riscv_batch_full().

- Corrected assertions in riscv_batch_get_dmi_read_op()
  and riscv_batch_get_dmi_read_data().

Cleanup:

- Simplified calloc() fail handling in riscv_batch_alloc().

- Added explicit NULL assignments in riscv_batch_alloc()
  for clarity and readability. Don't rely on calloc().

- Removed suffix `_u64` from riscv_*_fill_dm*() since it
  does not have any meaning.

- Renamed *dmi_write_u64_bits() to *get_dmi_scan_length()
  which better describes its purpose.

Change-Id: Id70e5968528d64b2ee5476f1c00e08459a1e291d
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2024-02-06 14:24:02 +01:00
Evgeniy Naydanov 24d71d7a72 target/riscv: set `state` and `debug_reason` in `riscv_halt_go_all_harts()`
If targets are in a halt group, and a target in the group reaches a
breakpoint, the target's state was able to remain `TARGET_RUNNING`.

Addresses issue #1010

Change-Id: I734bc6da71d289c4d05b417c8bf67a7d1a56574f
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-02-02 18:42:26 +03:00
Evgeniy Naydanov 16e7adbd9c Merge up to 9659a9b5e2 from upstream
Change-Id: I2fda9689d3465b3d8c8f3459b1ed954cb1d70fdc
2024-01-29 14:28:24 +03:00
Evgeniy Naydanov 1b0ffa97ea target: get_gdb_arch() accepts target via const pointer
The function in question does not need to change target state. It is a
target-type-dependant function, however, IMHO, it is safe to assume that
any target type would not need to change type-independant state of a
target to figure out the arch.

Change-Id: I607cb3aee6529cd5a97bc1200a0226cf6ef43caf
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8093
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-01-28 14:18:54 +00:00
Evgeniy Naydanov 41b5b5471b Revert "break from long loops on shutdown request"
This reverts commits 2e920a212f and
8dbb1250f5.

The reason is, after `openocd_is_shutdown_pending()` becomes true,
arbitrary command may be executed:
* In `target_destroy()` and the corresponding
  `target->type->deinit_target()`.
* In user-specifyed `pre_shutdown_commands` list.

Change-Id: Icd00d1d954cd45e255880a6f76c3a74c098d6a17
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-26 12:22:11 +03:00
Jan Matyas ec28cf03ae
Merge pull request #997 from en-sc/en-sc/priv-access
target/riscv: move read redirection for `priv` to `riscv-013.c`
2024-01-25 06:53:51 +01:00
Evgeniy Naydanov b503fdef02 target/riscv: report info about target during `poll`
Addresses issue #196.

Change-Id: I71146c7bc769cb9727e57da33e9f514eedef9ce4
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-24 10:43:51 +03:00
Evgeniy Naydanov ca3abcaa06 target/riscv: move read redirection for `priv` to `riscv-013.c`
The reason for the change is a conflict: `dcsr[5]` is `dcsr.v` in
current spec, but it is `dcsr.debugint` in 0.11. This causes `priv`
register to be read incorrectly.

Change-Id: If2d8fdcd8536afa4c7149c453101b00ce0df1ce0
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-23 17:50:01 +03:00
Jan Matyas 78a719fad3
Merge pull request #992 from en-sc/en-sc/remove-hart-count
target/riscv: remove `riscv_hart_count()`
2024-01-18 09:12:40 +01:00
Jan Matyas e6e9fbe2eb
Merge pull request #991 from en-sc/en-sc/dm-dmi-address-conversion
target/riscv: fix DM register address checks in `dm_read`/`dm_write`
2024-01-18 09:11:23 +01:00
Evgeniy Naydanov bb4c117d44 target/riscv: fix addressing in `dm_read`/`dm_wirte`
There was an error in `dm_read`/`dm_write`: DMI address was checked
against DM registers disregarding DM base address.

To solve the issue `dmi_address()` function was introduced.

Change-Id: Ia3be619417b5f5b53db5dfe302db05170d6787c9
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-16 18:14:58 +03:00
Evgeniy Naydanov ecb983a464 target/riscv: remove `riscv_hart_count()`
The motivalion for the change:
* `riscv_hart_count()` is used only once to print the value into the log
  during exmination.
* The returned value is a bit confusing: it's not the total number of
targets on the TAP. It is the number of targets accessable through the
same DM. So the name of the function is misleading.
* This value is already reported on `-d3` level.

So the function seems redundant and can be safely removed.

Change-Id: Iac9021af59ba8dba2cfb6b9dd15eebc98fe42a08
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-16 16:37:12 +03:00
Evgeniy Naydanov 8dbb1250f5 break from long loops on shutdown request
In loops that typically take longer time to complete, check if there is
a pending shutdown request. If so, terminate the loop.

This allows to respond to a signal requesting a shutdown during some
loops which do not return control to main OpenOCD loop.

Change-Id: Iace0b58eddde1237832d0f9333a7c7b930565674
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-01-09 12:36:05 +03:00
Parshintsev Anatoly aded275b70 rename dbgbuf to progbuf
Change-Id: I29e2192d5ce9d0f13010d8a09bd4ef50f5c8844b
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-12-22 11:35:23 +03:00
Parshintsev Anatoly 928f10a537 introduce execution status for riscv_program
Change-Id: I3b283b49dea88a6f3d2159be3c9f6c6da604aa9e
Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
2023-12-22 11:35:18 +03:00
Tim Newsome af786c0eca
Merge pull request #963 from kr-sc/kr-sc/no-free-triggers
When an attempt to set watchpoint fails because there is no free triggers OpenOCD reports "unknown error"
2023-11-17 09:18:44 -08:00