0b027a2854
Code cleanup. Bump debug_defines.h version
2018-04-16 17:20:31 -07:00
bf0ffff1db
Fix issue with COMMAND_PARSE_NUMBER
2018-04-13 16:09:57 -07:00
065671b311
Code style cleanup
2018-04-13 11:20:12 -07:00
1ba3986eb7
More test/SBA RTL debug
2018-04-12 12:26:54 -07:00
a9b8820916
Checkpoint: debugging tests
2018-04-11 18:10:48 -07:00
50cd4203a5
Fix more style issues with previous commit
2018-04-11 14:41:00 -07:00
4191505b76
Fix style issues with previous commit
2018-04-11 14:38:51 -07:00
cc98a14839
Added address alignment test, code fixups from review
2018-04-11 14:26:16 -07:00
836bd7cb69
Fix sign compare compiler error
2018-04-09 11:55:46 -07:00
c2c52c89b1
Fix some build issues
2018-04-09 11:38:41 -07:00
99f2f5a272
Change #ifdef SIM_ON to be a run-time arg
2018-04-09 11:26:31 -07:00
de329f4004
Fixed style issues in previous commit.
2018-04-09 10:54:21 -07:00
a9b2277574
Add #ifdef to only enable sbbusyerror test in simulation.
2018-04-09 10:51:53 -07:00
7c6f6d79bc
Fixed more style issues
2018-04-05 17:59:43 -07:00
d471fff3db
Fixed build issues
2018-04-05 17:57:53 -07:00
ada78cae11
Checkpoint: fix even more code style issues
2018-04-05 16:49:00 -07:00
8c8bed878c
Checkpoint: fix some more code style issues
2018-04-05 16:42:28 -07:00
761aaeba98
Checkpoint: fix some code style issues
2018-04-05 16:39:33 -07:00
3bdb8b29a8
Checkpoint: finish debug of tests, working on hitting sbbusyerror case
2018-04-05 16:31:09 -07:00
c5a8e1cf4c
Initial commit of tests for SBA feature
2018-04-04 13:50:17 -07:00
52eabbd2a5
Add `riscv set_prefer_sba`
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This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.
Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
ca13327abf
Merge pull request #227 from riscv/fix_build
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Fix build, broken by b7c5c5d228
2018-03-19 13:40:48 -07:00
d5b450c508
Fix build, broken by b7c5c5d228.
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Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
2018-03-19 12:56:05 -07:00
b7c5c5d228
Merge pull request #225 from riscv/old_bus2
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Support v0 System Bus Access
2018-03-19 12:11:28 -07:00
3ddbbd525d
Merge pull request #222 from riscv/dmi_commands
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Add riscv dmi_read/dmi_write commands.
2018-03-15 11:32:33 -07:00
68a6812a41
Use TARGET_PRIxADDR instead of PRIx64.
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Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
2018-03-09 18:02:18 -08:00
075610d495
Support v0 system bus access
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This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214 . This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.
I have not tested the new code because I don't have a target. It does
not cause any regressions.
Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
2018-03-09 18:02:18 -08:00
fd9de02fac
Merge pull request #221 from riscv/reg_running
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Error instead of asserting on reg access failure
2018-03-07 12:22:33 -08:00
c54da11679
Merge pull request #220 from riscv/reg_error
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Remove errors when accessing a non-existent register
2018-03-07 12:22:15 -08:00
298d885fdf
Merge pull request #223 from riscv/upstream
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Match upstream.
2018-03-07 12:20:35 -08:00
c10c570dca
Fix cut and paste error message.
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Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
3d571df785
Match upstream.
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Change-Id: I3d8b3cb9913ea7d09a5981f6d11b0af67ef0c9c7
2018-03-06 13:07:34 -08:00
ddb894edf6
Add riscv dmi_read/dmi_write commands.
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Mostly addresses #207 .
Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.
Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
509e0e4715
Error instead of asserting on reg access failure
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Instead of asserting, return error when an abstract register access
fails on running target.
Fixes #201
Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
2018-03-02 20:24:58 -08:00
84c0fdd5d1
Don't always error if a debug program fails
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This is often expected, and the calling code should decide whether to
emit an error or not.
Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
2018-03-02 20:02:32 -08:00
1d00d03dc0
Remove unable to read register error message
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It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.
Fixes #176
Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
2018-03-02 19:41:31 -08:00
5767fa8e04
Merge pull request #219 from riscv/propagate_errors
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Only propagate register errors on some targets
2018-03-02 12:07:55 -08:00
1d9418fbb0
Only propagate register errors on some targets
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Without this change, connecting to ARM targets is impossible.
Fixes #115 .
Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs
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target/riscv: add some switch fallthrough comments
2018-02-28 12:31:22 -08:00
d388f1cbb2
Merge pull request #218 from riscv/auth
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Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
2018-02-28 09:20:31 -08:00
39716b15ab
Fix authentication for multi-core targets.
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When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.
Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
2018-02-27 14:22:06 -08:00
10108b623d
Add `authdata_read` and `authdata_write` commands.
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They can be used to authenticate to a Debug Module.
There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.
Example usage (very simple challenge-response protocol):
```
init
set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
reset halt
```
Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
9033d99491
Merge pull request #217 from riscv/disable_target64
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build with --disable-target64
2018-02-26 12:06:47 -08:00
3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
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Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
d570f89303
target/riscv: add some switch fallthrough comments
2018-02-20 14:31:31 +01:00
6b02ab4196
Fix build with --disable-target64
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Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
cf895486b6
Add a build with --disable_target64
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Change-Id: Ibe52a678ab7b8145ffaa54dce38149aa95bdb48c
2018-02-19 14:25:48 -08:00
352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
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Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
6cbb45f7f1
Merge pull request #205 from riscv/update
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Merge changes from upstream.
2018-02-08 11:36:11 -08:00
2e415b3930
Merge pull request #210 from riscv/reset_before_hart_enum
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complete reset before writing to hartsel field
2018-02-07 18:35:06 -08:00
Ryan Macdonald
Tim Newsome
Kaspar Schleiser
Gleb Gagarin