Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Provide an "armv7a disassemble" command. Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60
lean up some loose ends with the ARM disassembler
- Add a header comment describing its current state and uses
and referencing the now-generally-available V7 arch spec
- Support some mode switch instructions:
* Thumb to Jazelle (BXJ)
* Thumb to ThumbEE (ENTERX)
* ThumbEE to Thumb (LEAVEX)
- Improve that recent warning fix (and associated whitespace goof)
- Declare the rest of the internal code and data "static". A
compiler may use this, and it helps clarify the scope of these
routines (e.g. what changes to them could affect).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60
that were added after ARMv5TE was defined:
- ARMv5J "BXJ" (for Java/Jazelle)
- ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)
Compile-tested. This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).
ARMv6 instructions known to be mis-handled by this disassembler
include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2
git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
For ARMv4/ARMv5:
- better command parameter error checking
- don't require an instruction count; default to one
- recognize thumb function addresses
- make function static
- shorten some too-long lines
For Cortex-M3:
- don't require an instruction count; default to one
With the relevant doc updates.
---
Nyet done: invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2624 b42882b7-edfa-0310-969c-e2dbd0fdcd60
reset operations. Maybe they can't; or it's a "not yet" thing.
Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2620 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2613 b42882b7-edfa-0310-969c-e2dbd0fdcd60
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from Øyvind, and cleanup from Dave.)
This code has mainly been developed and tested against R1606, it has
been built and tested against R2294 where it runs but step and resume
commands are broken due to regression (which should be fixed now).
This code is really written for OMAP3530. It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection. The OMAP3530 DAP exposes two memory access ports:
- Port #0 is connected to L3 interconnect (the main bus) with
passthrough to the L4 EMU bus ... so it will be used for most
memory accesses.
- Port #1 is connected to a dedicated debug bus (L4 EMU), with
access to L4 Wakeup, and holds the ROM table ... so it must
be used for most debug and control operations.
The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code. Having access to another Cortex-A8
implementation would help get that right.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2609 b42882b7-edfa-0310-969c-e2dbd0fdcd60
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from Øyvind and Dave.)
The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.
The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions. Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too. There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2608 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch
GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler. LDREX and STREX are not
issued by GCC without inline assembly.
This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled. Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- spell "address" right
- list bp/wp params as optional
And make those source lines wrap at sane margins.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- AIRCR_SYSRESETREQ is generic; use it on any system where
SRST won't fly, not just on Stellaris-based ones.
- Reformat and improve comments about the Stellaris quirk; and
xref the only public docs (an email) about the issue.
It seems that *most* Stellaris chips have this problem. Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Simplify dumping of register lists by only printing cached values
if they are marked as valid. Most of the time, they are invalid;
so printing *any* value is just misleading.
Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
display them as 32 bits unless that's their true size.
(Removes some confusion.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.11 Data processing (shifted register)
The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes. There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
ARMv7-M arch manual:
A5.3.1 Data processing (modified immediate)
A5.3.3 Data processing (plain binary immediate)
A5.3.4 Branches and miscellaneous control
and other (immediate) encodings referenced there. Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:
A5.3.12 Data processing (register)
A5.3.13 Miscellaneous operations
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, and divide
The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Dump SP on poll, and show whether it's MSP or PSP.
Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.
Shrink some lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Clean up treatment of registers in ARMv7-M and Cortex-M3.
- At the arch level:
* Just list registers and names; don't impose core-specific
policy about how they are accessed.
* Each register has a symbol.
* Remove the register mode field (irrelevant to debugger)
- At the core/implementation level:
* Just map the registers to their relevant access methods;
don't require the arch level to say how that should work
(cores other than Cortex-M3 could do it differently).
* Don't use undefined bits from register 20.
* Use register IDs that are part of the ARMv7-M interface.
In short, there's now a real distinction between the arch
and core layers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Minor updates to the Thumb2 disassembly:
- Bugfixes:
* Distinguish branch from misc via "!=" not "=="
* MRS register shift is 8 bits (vs MSR being 16)
- Format tweaks:
* CPS needed tab (not space)
* add commma before some shifts
* add space after comma in LDM/STM
* use ".W" width spec on various instructions
git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).
git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c. There should be no
change in functionality here. (From Magnus.)
Minor style cleanup: whitespace, line length, etc. Update spec
references to use docs which are currently available. (From Dave.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.5 Load/store multiple
The preferred PUSH/POP syntax is shown when appropriate.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2539 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More instructions decoded:
A5.3.14 Multiply, and multiply accumulate
A5.3.15 Long multiply, long multiply accumulate, divide
The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2538 b42882b7-edfa-0310-969c-e2dbd0fdcd60
More Thumb2 32-bit opcode support:
A5.3.10 Store single data item
Byte, word, halfword. Offset, pre-index, post-index. And
a "make like you're unprivileged" option when using small
immediate offsets.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2537 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Print old-style Thumb NOP instructions as such. (GCC uses "mov r8, r8"
instead of the architected NOP which is new in Thumb2.)
git-svn-id: svn://svn.berlios.de/openocd/trunk@2536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make disassembly of the Thumb load-literal instruction show the
address of the literal being loaded (so users can avoid doing
that math themselves). Add and use an Align(PC,4) utility.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2535 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.3 Data processing (plain binary immediate)
These use mostly twelve bit literals, but there are also bitfield
and saturated add primitives.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2534 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle more 32-bit instructions:
A5.3.1 Data processing (modified immediate)
My small sample shows GCC likes to use many of these instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2533 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Make the Thumb2 disassembler handle a bunch of 32-bit instructions:
A5.3.4 Branches and miscellaneous control
Note that this shifts some responsabililty out of helper functions,
making the code and layout simpler for 32-bit decoders: they only
need to know how to format the instruction and its parameters.
Also, technical note: with this patch, Thumb1 decoders could now
call the Thumb2 decoder if they wanted to get nicer treatment of
the exiting 32-bit B/BLX instructions.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2532 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Change layout of Thumb disassembly to work better with Thumb2:
- Move opcode to the left, allowing space for four hex bytes:
* after address, two spaces not one tab (taking 6 spaces)
* after 2-byte opcode, four spaces before tab
- Also, after opcode mnemonic use a tab not a space, to make
operands line up
Sample output (after some patches decoding a few 32-bit instructions):
0x00003e5a 0xf4423200 ORR r2, r2, #131072 ; 0x20000
0x00003e5e 0x601a STR r2, [r3, #0x0]
0x00003e60 0x2800 CMP r0, #0x00
0x00003e62 0xd1f3 BNE 0x00003e4c
0x00003e64 0xf008fa38 BL 0x0000c2d8
The affected lines of code now wrap at sane margins too.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2531 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Initial support for disassembling Thumb2 code. This works only for
Cortex-M3 cores so far. Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.
- Update the 16-bit Thumb decoder:
* Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
by ARMv6. (It already seems to treat CPY as MOV.)
* Understand CB, CBNZ, WFI, IT, and other opcodes added by
in Thumb2.
- A new Thumb2 instruction decode routine is provided.
* This has a different signature: pass the target, not the
instruction, so it can fetch a second halfword when needed.
The instruction size is likewise returned to the caller.
* 32-bit instructions are recognized but not yet decoded.
- Start using the current "UAL" syntax in some cases. "SWI" is
renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".
- Define a new "cortex_m3 disassemble addr count" command to give
access to this disassembly.
Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch correctly identifies a running target.
Patch made a tad more palatable by David Brownell <david-b@pacbell.net>
git-svn-id: svn://svn.berlios.de/openocd/trunk@2510 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Remove some bogus warnings during server startup for ARM926ejs
targets that were already halted for debug ... e.g. started up
a freshly built instance.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2417 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This is minimal patch to support FA526 ARMv4 compatible core.
Since it is very similar to ARM920T I tried to reuse as much
code as possible.
CPU and board configs will follow soon.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2292 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix parsing bugs for "$target_name mww addr data [count]" ... it was
always requiring the count, instead of just defaulting it to one.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2263 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Extend the internal JTAG event handlers to cover enable/disable,
and use those events to make sure that targets get "examined" if
they were disabled when the scan chain was first set up:
- Remove "enum jtag_tap_event", merge with "enum jtag_event",
so C code can now listen for TAP enable/disable events.
- Report those events so they can trigger callbacks.
- During startup, make target_examine() register a handler to
catch ENABLE events for any then-disabled targets.
This fixes bugs like "can't halt target after enabling its TAP".
One class of unresolved bugs: if the target has an ETM hooked
up to an ETB, nothing activates the ETB. But starting up the
ETM without access to the ETB registers fails...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2251 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Fix some polling issues:
- Don't background-poll disabled TAPs ... this was just a bug
waiting to happen. (And then it happened!)
- Don't fail command line polls of disabled taps; that's not any
kind of error, it's just that you can't do much. But do show
that tap-disabled status.
- Spell "continuous" correctly in the variable name. ;)
Not resolved by this patch: the need for an interlock whereby
other code (like the JTAG layer) can block all other access to
the JTAG layer, e.g. while enabling or disabling TAPs. And
that interlock needs to be timer-safe...
git-svn-id: svn://svn.berlios.de/openocd/trunk@2247 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Make fast_load_image use the helper coverage the standard load_image.
- Improve whitespace in the moved lines.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2239 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Simplify argument parsing logic using switch statement.
- Use parse_u32 to ensure all values parse properly.
- Return syntax error when mode argument fails to parse.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2236 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return syntax error if remove called without one argument.
- Use parse_u32 to ensure address and length arguments parse properly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2235 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Change: All local variable types are now unsigned.
- Use parse_u32 to ensure address and value parse properly.
- Use parse_uint to ensure count parses properly.
- Move variables to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2231 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use parse_u32 and parse_uint for address and count, respectively.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2230 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Make argument check use parse_uint to ensure value parses properly.
- Move variable declarations to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2228 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Use unsigned type for delay variable.
- Use parse_uint to ensure delay argument parses properly.
- Bug fix: Return syntax error if more than one argument is given.
- Bug fix: Return syntax error when argument fails to parse.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2227 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move the mips32_..._read_mem calls to top-level of read_mem function.
- Change: Only perform mips_m4k_read_mem conversion when retval == ERROR_OK.
- Prevents pointless conversions of bogus read values after failures.
- Eliminate retval variable from mips_m4k_write_mem; return directly.
- Move declaration of retval variable to point of first use.
- Remove the now redundant switch statements testing size:
- argument sanitizing already covers these cases.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2220 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This patch helps fix MIPS big endian (elf32-tradbigmips) targets.
If "-endian big" is not set in target create, the endianess defaults to
little. mw and md commands will still work, but binary file loads will
have the incorrect word order loaded into memory.
The EJTAG processor access data register (PrAcc) is little endian
regardless of the CPU endianness; it is always loaded LSB first. This
is confirmed by the fact that mips_ejtag_drscan_32() uses buf_set_u32()
to load the scan field; buf_set_u32() is a little-endian formatter. For
big endian targets, data buffers have to be modified so the LSB of each
u32 or u16 is at the lower (first) memory location. If the drscan
out_value word order is set using buf_set_u32() then it makes sense to
also fixup the in_value with buf_get_u32(); a symmetry argument. This
has no affect on little endian hosts.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2219 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Original patch submitted by David Claffey [dnclaffey@gmail.com].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2202 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return a syntax error if the wrong number of arguments are given.
- Add handle_bp_command_list() and handle_bp_command_set().
- Use temporary addr variable to eliminate redundant strtoul() calls.
- Place variable declarations at their point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2196 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add target_timer_callback_periodic_restart and target_call_timer_callback.
- Clean up and simplify logic that determines whether to call each callback.
- Move variable declarations to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2195 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add a doxygen block to simplify logic.
- Move declarations to point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2194 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Return syntax error unless exactly one argument is passed.
- Move variable declaration to point of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2193 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Return syntax error if more than one argument is given.
- Move variables to location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2192 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Eliminate redundant calls to target_resume with addr temp variable.
- Place variables at location of first use.
- Fix minor whitespace issues.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2191 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bug fix: return syntax error when more than one argument is given.
- Eliminate redundant calls to step callback with addr temp variable.
- Place variables at location of first use.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2190 b42882b7-edfa-0310-969c-e2dbd0fdcd60
other server configuration. Explain what it's about;
reference the related "$target_name curstate" method.
Update "poll" output to report whether background polling
is enabled or not.
Also fix a small typo; PC's have "complementary" tools.
Some have also "complimentary" ones; but not all.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2178 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Update handle_reset_config_command in tcl.c to use new helpers.
- Replace direct accesses in JTAG interface and target drivers.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2161 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add accessor functions to return their value.
- Use new SRST accessor in cortex_m3.c and mips_m4k.c
git-svn-id: svn://svn.berlios.de/openocd/trunk@2157 b42882b7-edfa-0310-969c-e2dbd0fdcd60
should return the "is it backed up?" flag, not the work area size.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2108 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Don't let disabled TAPs be set as the current target
- Improve "targets" output:
* Remove undesirable "chain position" number; we discourage using them
* TAP and Target column updates:
+ make them long enough for current usage
+ improve labels, removing guesswork
+ "TapName" label patches scan_chain output
* Highlight the "current" target
* Display "tap disabled" as a new pseudo-state
* Update docs accordingly
git-svn-id: svn://svn.berlios.de/openocd/trunk@2107 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Let disabled targets be ignored during normal operation:
- In target_examine(), ignore disabled TAPs
- Reset handling must not poke at them either:
* fail $target_name arp_* operations on disabled TAPs
* in startup.tcl, don't even issue the arp_* wait ops
ZW: removed superfluous braces from the patch to target.c.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2100 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- set TAR size to 12 bits for Cortex-M3.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2051 b42882b7-edfa-0310-969c-e2dbd0fdcd60
this fn has something to do with the queue, which it does not as such.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2050 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- change SWJDP_IR/DR_APACC to DAP_IR/DR_APACC to conform with ARM_ADI docs.
- add swjdp->memaccess_tck field and code for extra tck clocks before accessing memory bus
- Set default memaccess value to 8 for Cortex-M3.
- Add dap memaccess command.
- document all armv7 dap cmds.
- Original patch submitted by Magnus Lundin [lundin@mlu.mine.nu].
git-svn-id: svn://svn.berlios.de/openocd/trunk@2005 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move definition of 'struct target_type_s' into new 'target_type.h' file.
- Forward delclaration remains in target.h, with comment pointing to new file.
- Replaces #define with #include in source files.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1971 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- use continuations to break long lines of variable assignments
- makes these variables more patch-friendly and conform to style guide
git-svn-id: svn://svn.berlios.de/openocd/trunk@1970 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add DEFINE_TARGET_TYPE_S symbol in files that need it defined.
- Forward declare 'struct target_type_s' only, unless that symbol is defined.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1969 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->{add,remove}_{break,watch}point.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1967 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all accesses to target->type->name.
- add documentation in target_s to warn not to access field directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1966 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->get_gdb_reg_list.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1964 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->bulk_write_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1963 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replace all checks of target->type->examined with target_was_examined().
- replace all setting of target->type->examined with target_set_examined().
- replace clearing of target->type->examined with target_reset_examined().
- add documentation in target_s to warn not to access field directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1962 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->run_algorithm.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1961 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->write_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1960 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- replaces all calls to target->type->read_memory.
- add documentation in target_s to warn not to invoke callback directly.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1959 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- fix buffer overrun in mdw; final '\0' would overflow the output buffer.
- return ERROR_COMMAND_SYNTAX_ERROR instead of ERROR_OK if:
- less than one argument is provided
- the command is called with a name other than mdb, mdh, or mdw.
- factor all command output into new handle_md_output function
git-svn-id: svn://svn.berlios.de/openocd/trunk@1958 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- wordsize will always be 1, 2, or 4 due to preceeding switch statement.
- move call to keep_alive after successful writes, not upon failures
git-svn-id: svn://svn.berlios.de/openocd/trunk@1953 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Provide basic documentation on the ARM ETM and ETB trace commands.
Fix minor goofs in registration of the ETM commands; and whitespace
issues in the proof-of-concept oocd_trace code. (Plus include a
ref to Dominic's email saying that it's just proof-of-concept code.)
Note that I'm still not sure whether the ETM support works. But
documenting how it's expected to work should help sort out which
behaviors are bugs, which will help get bugs patched.
ZW: whitespace changes were split out of this patch but will follow.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1945 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- cut out the "unknown EmbeddedICE version" message with Feroceon
git-svn-id: svn://svn.berlios.de/openocd/trunk@1934 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Move src/target/{interface,target,board,test}/ into src/tcl/
- Remove existing rules in src/Makefile.am and src/target/Makefile.am.
- Add Makefile.am handling of *.cfg and *.tcl files in top Makefile.am:
- Add dist-hook to include such files under src/tcl in the distribution.
- Add install-data-hook to install contents of '$(top_srcdir)/src/tcl/'.
- Add uninstall-hook to remove the installed script files.
- Change paths to (un)install script files in '$(pkgdatadir)/scripts'.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1918 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This was forgotten here. All other LPC targets use
this option.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1906 b42882b7-edfa-0310-969c-e2dbd0fdcd60
When the CPU is in the WFI state, the JTAG interface simply doesn't
respond at all and initial tap examination simply fails. Let's simply
do it again when we come around to assert nSRST.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1905 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Update two oddball NAND commands to work with {offset, length}
instead of block numbers, matching the other commands as well
as usage in U-Boot and the Linux-MTD utilities.
Document them accordingly. Update the single in-tree use of
those commands (sheevaplug).
ALSO:
(a) Document the current 2 GByte/chip ceiling for NAND chipsize.
(32 bit offset/length values can't represent 4 GBytes.) Maybe
after the upcoming release, the code can switch to 64-bits.
(b) The "nand check_bad_blocks" should report "bad" blocks. They
are not "invalid" blocks; they're "bad" ones.
(c) Tweak the "nand info" command to handle the "no arguments"
case sanely (show everything, instead of showing garbage) and
not listing the blocksize in hex kbytes (duh).
git-svn-id: svn://svn.berlios.de/openocd/trunk@1904 b42882b7-edfa-0310-969c-e2dbd0fdcd60
NAND support for DaVinci-family drivers, with HW ECC support.
Declare the NAND chip on the DM355 EVM board.
Currently tested on DM355 for Linux interop using the standard
large page (2KB) chip in the EVM socket; "hwecc1" and "hwecc4"
work fine. (Using hwecc4 relies on patches that haven't quite
made it through the Linux-MTD bottlenecks yet.)
Not yet tested: 1-bit on small-page (although it's hard to see
how that could fail); 4-bit on small page (picky layout issues);
the "hwecc_infix" mode (primarily for older boot ROMs; testing
there is blocked on having new bootloader code).
git-svn-id: svn://svn.berlios.de/openocd/trunk@1903 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Improve support for the DM355 EVM board, and eventually other boards based
on DaVinci chips:
- Provide generic "davinci.cfg" to hold utilities that can be reused by
different chips in this family. Start with PINMUX, PSC, and PLL setup.
- DM355 chip support updates: provide a dictionary with chip-specific
symbols, load those utilities.
- Create a new dm355evm board file, with a reset-init event handler
which uses those utilities to set up PLLs and clocks, configure the
pins, and improve the JTAG speed limit.
Also a minor tweak: provide a virtual address for the work area, matching
what the very latest kernels do. It's probably unwise to use OpenOCD while
the MMU is active though.
The DRAM isn't yet accessible, but NAND access is mostly ready.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1881 b42882b7-edfa-0310-969c-e2dbd0fdcd60
the key command_*() helper functions, fixng the bugs that turned up.
Several of these bugs were from misuse of PRIi64; that's for 64-bit
integers, NOT for "long long" or "u64" (which work best with %lld).
git-svn-id: svn://svn.berlios.de/openocd/trunk@1873 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Bring the mips step/resume interrupt handling inline with the
rest of openocd.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1850 b42882b7-edfa-0310-969c-e2dbd0fdcd60
- Add libtoolize step too bootstrap script; creates ltmain.sh script.
- Add AC_PROG_LIBTOOL to configure.in to add libtool support to build.
- Change Makefile.am library rules from static (_a) to libtool (_la).
- Install libopenocd.{la,so,a} in $(libdir); update openocd link rules.
- Extend MAINTAINERCLEANFILES in top-level Makefile.am to remove ltmain.sh.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1695 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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