This adds the core of the UART-Wishbone bridge. The protocol has
a variable-length address phase to help reduce overhead. Multiple
in-flight commands are not supported, although this could be resolved
with some FIFOs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Signals modified by cocotb tasks may not be visible to other tasks on
the same clock cycle. This was causing issues for recv_packet, because
it might not see the same values for ready/valid driven by ClockEnable
that the DUT sees. This was worked around by sampling on the RisingEdge.
However, this can cause recv_packet to miss data. Fix this by using
RisingEdge for ClockEnable, so everything can be sampled on the
FallingEdge.
Fixes: 52325f2 ("Add AXI stream replay buffer")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add the recieve half of the UART. It's more or less the inverse of the
transmit half, except we manage the state explicitly. I originally did
this in hopes that yosys would recode the FSM, but it doesn't like the
subtraction in the D* states. I left in the async reset anyway since it
reduces the LUT count.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Export recv_packet for use by other testbenches. This is mostly
straightforward, except we need the ability to manually specify when
last should be asserted (to handle replays).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
I join everyone and their mother in creating my own UART. 8n1 only, and 2
baud rates. Accepts AXI-stream.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Icarus verilog complains if you are sensitive to every element in an
array:
rtl/mii_elastic_buffer.v:78: warning: @* is sensitive to all 5 words in array 'data'.
This makes sense if you intend to synthesize this array to a block RAM,
but not really if it's supposed to be registers. Silence this warning.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add some modules to test with which were previously missing.
Fixes: b68e131 ("Add a basic hub")
Fixes: 0495ae3 ("Add TX MAC (most of it)")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds an example of how to integrate the hub into a design. For the
moment, wishbone is disabled, but I plan to add a uart bridge in the
future.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Create a list of extensions to clean, and then use wildcards to remove
the files. This will make it easier to clean other (nested) directories.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Export some status signals which can be used for LEDs. Hopefully this
will deliver an authentic blinkenlights experience.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a basic hub wrapper module which incorperates the core
introduced in b68e131 ("Add a basic hub"). For each port, it
instantiates a phy (itself using a phy_internal wrapper) and an elastic
buffer. A WISHBONE parameter is used to control whether to instantiate a
wishbone interface. When disabled, we just respond to any request with
err. I've ommitted a separate testbench for phy_internal, since it is
much easier to create a smoke test using the hub interface.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The flip-flops internal to the SB_IO can't have initial values and
can't be reset. So before the first clock the data out will be X. This
results in a simulation-synthesis mismatch, as sd_delay will be wrong
for one clock cycle. Fix this by removing the SB_IO cell, as the timing
of this signal isn't critical.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a simple wishbone mux. The idea is that each slave gets its
own address bit. This lends itself to extemely simple address decoding,
but uses up address space quickly. In theory, we could also give larger
addres space to some slaves, but currently lower bits have priority. The
testbench is also very simple. Since everything is combinatorial, we can
determine the outputs from the inputs exactly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
There are several places where memories are used for parametrization
purposes, but I intend them to be synthesized to registers. Silence
warnings about them by explicitly annotating these variables.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Using -s /dev/stdin will add a dependency on it, and /dev/stdin is
always considered newer than the synthesis output. Just use multiple
-p options.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This module will make it easier to observe internal signals which would
otherwise be too short to see, or would trigger too fast to distinguish.
Continuous triggered will cause blinking, so signals which are expected
to be high for a while (e.g. level-based and not edge-based) should not
use this module.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
In order to move data between MIIs without implementing a MAC, we need
some kind of elastic buffer to bring the data into the transmit "clock
(enable) domain." Implement one. It's based on a classic shift-register
FIFO, with the main difference being the MII interfaces and the
elasticity (achieved by delaying asserting RX_DV until we reach the
WATERMARK). We use a register-based buffer because we only need to deal
with an under-/over-flow of 5 or so clocks for a 2000-byte packet. The
per-stage resource increase works out to 6 FFs and 1 LUT, which is
pretty much optimal.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
In addition to PNR-ing for per-module, post-placement simulation, we
also want to be able to do PNR for the purposes of generating a
bitstream. Refactor things a bit so we can (mostly) reuse the same
command line.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a basic clause 27 repeater (hub), mostly for test purposes.
It's effectively just the state machine in figure 27-4 and nothing else
(e.g. no partitioning or jabber detection). This is surprisingly simple.
Unfortunately, yosys doesn't allow memories in port declarations, even
for systemverilog. This complicates the implementation and testbench,
since we have to do the slicing ourselves. This is particularly awful
for the testbench, since
module.signal[0].value != module.signal.value[0]
and module.signal can't be indexed by slices, and module.signal.value is
big endian (ugh ugh ugh). There is no clean solution here.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds support for half-duplex. This is mostly done by predicating
col and crs on half_duplex. In one place we need to go to IPG_LATE
directly (although we could go to IPG_LATE like FCS with no loss of
standard compliance).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
get_sim_time can return floating point values. This will cause tests to
fail since there is an epsilon of error. Fix this by timing things in
steps (which is always an int).
Fixes: 0495ae3 ("Add TX MAC (most of it)")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We might not release rst synchronously if clk was already high. Fix this
by forcing clk to z.
Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Including registers which are not reset in an asynchronous reset process
causes active-low clock-enable flip-flops to be synthesized. This is an
unusual configuration, incurs overhead, and isn't what we wanted to do
anyway. Use a separate process.
While we're at it, sort the bottom half of the if to match the top.
Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The 2 ns delay when reading from a BRAM makes it hard to close timing,
since buf_err affects the state machine. Address this by not acting on
errors for a clock cycle. We will output bad data for a cycle, but we
are going to corrupt the FCS anyway so it doesn't matter. We also have
to check for errors in the PAD/FCS states, to ensure they don't slip
past.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
If we ever see an error, we shouldn't retry if we get a collision at the
same time, as we will just have to jam next time. Test for this case
instead.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Allow delaying the last byte to make it easier to exactly time when the
MAC sees the byte. This way, we can test to ensure that everything works
even when valid is only high for one cycle. We can't change signals
once valid goes high, so this is the only way to ensure this kind of
timing.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We don't need to delay after sending the last byte, and it makes it more
difficult to time subsequent packets correctly.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
We only care about backoff when state=BACKOFF. We can simplify the
calculation by defaulting to loading lfsr into backoff, and special
casing things for state=BACKOFF.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds the transmit half of a MAC, supporting 100M and half-duplex.
It's roughly analogous to the axis_(x)gmii_tx modules in Alex
Forencich's ethernet repo. I've taken the approach of moving all state
into the state variable. All decisions are made once and have a
different state for each path. For example, instead of checking against
a "bytes_sent" variable to determine what to do on collision, we have a
different state for each set of actions.
This whole module is heinously complex, especially because of the many
corner cases caused by the spec. I have probably not tested it nearly
enough, but the basics of sending packets have mostly had the bugs wrung
out.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson