Add hub
This adds a basic hub wrapper module which incorperates the core
introduced in b68e131 ("Add a basic hub"). For each port, it
instantiates a phy (itself using a phy_internal wrapper) and an elastic
buffer. A WISHBONE parameter is used to control whether to instantiate a
wishbone interface. When disabled, we just respond to any request with
err. I've ommitted a separate testbench for phy_internal, since it is
much easier to create a smoke test using the hub interface.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson
parent
cc29d2050c
commit
b351beb9a0
1
Makefile
1
Makefile
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@ -119,6 +119,7 @@ endef
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MODULES += axis_replay_buffer
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MODULES += descramble
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MODULES += hub
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MODULES += led_blinker
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MODULES += mdio
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MODULES += mdio_io
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@ -0,0 +1,170 @@
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// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module hub (
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input clk_125,
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input clk_250,
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input [PORT_COUNT - 1:0] indicate_data,
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input [PORT_COUNT - 1:0] signal_detect,
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output [PORT_COUNT - 1:0] request_data,
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/* Wishbone management */
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output wb_ack, wb_err,
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input wb_cyc, wb_stb, wb_we,
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input [PORT_COUNT + 5 - 1:0] wb_addr,
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input [15:0] wb_data_write,
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output [15:0] wb_data_read,
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/* Other status (for LEDs) */
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output reg collision, transmitting,
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output [PORT_COUNT - 1:0] link_status,
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output [PORT_COUNT - 1:0] receiving
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);
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parameter WISHBONE = 1;
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parameter PORT_COUNT = 4;
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parameter ELASTIC_BUF_SIZE = 3;
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parameter ENABLE_COUNTERS = 1;
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parameter [23:0] OUI = 0;
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parameter [5:0] MODEL = 0;
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parameter [3:0] REVISION = 0;
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localparam MII_100_RATIO = 5;
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reg buf_ce, tx_ce;
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wire collision_next, transmitting_next;
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wire [PORT_COUNT - 1:0] rx_ce, rx_dv, rx_er, tx_en, tx_er, buf_dv, buf_er, col, crs;
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wire [PORT_COUNT * 4 - 1:0] rxd, txd, buf_data;
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hub_core #(
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.PORT_COUNT(PORT_COUNT)
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) hub (
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.clk(clk_125),
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.rx_dv(buf_dv),
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.rx_er(buf_er),
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.rxd(buf_data),
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.tx_en(tx_en),
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.tx_er(tx_er),
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.txd(txd),
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.jam(collision_next),
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.activity(transmitting_next)
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);
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wire [PORT_COUNT - 1:0] bus_ack, bus_err, bus_cyc, bus_stb, bus_we;
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wire [5 * PORT_COUNT - 1:0] bus_addr;
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wire [16 * PORT_COUNT - 1:0] bus_data_write, bus_data_read;
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generate if (WISHBONE) begin
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wb_mux #(
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.ADDR_WIDTH(5),
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.DATA_WIDTH(16),
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.SLAVES(PORT_COUNT)
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) mux (
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.m_ack(wb_ack),
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.m_err(wb_err),
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.m_cyc(wb_cyc),
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.m_stb(wb_stb),
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.m_we(wb_we),
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.m_addr(wb_addr),
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.m_data_write(wb_data_write),
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.m_data_read(wb_data_read),
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.s_ack(bus_ack),
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.s_err(bus_err),
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.s_cyc(bus_cyc),
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.s_stb(bus_stb),
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.s_we(bus_we),
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.s_addr(bus_addr),
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.s_data_write(bus_data_write),
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.s_data_read(bus_data_read)
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);
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end else begin
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assign wb_ack = 0;
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assign wb_err = wb_cyc && wb_stb;
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assign bus_cyc = {PORT_COUNT{1'b0}};
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assign bus_stb = {PORT_COUNT{1'b0}};
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end endgenerate
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genvar i;
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generate for (i = 0; i < PORT_COUNT; i = i + 1) begin : port
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phy_internal #(
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.WISHBONE(WISHBONE),
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.OUI(OUI),
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.MODEL(MODEL),
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.REVISION(REVISION)
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) phy (
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.clk_125(clk_125),
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.clk_250(clk_250),
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.indicate_data(indicate_data[i]),
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.signal_detect(signal_detect[i]),
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.request_data(request_data[i]),
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.mii_tx_ce(tx_ce),
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.mii_tx_en(tx_en[i]),
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.mii_tx_er(tx_er[i]),
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.mii_txd(txd[i * 4 +: 4]),
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.mii_rx_ce(rx_ce[i]),
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.mii_rx_dv(rx_dv[i]),
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.mii_rx_er(rx_er[i]),
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.mii_rxd(rxd[i * 4 +: 4]),
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.wb_ack(bus_ack[i]),
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.wb_err(bus_err[i]),
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.wb_cyc(bus_cyc[i]),
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.wb_stb(bus_stb[i]),
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.wb_we(bus_we[i]),
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.wb_addr(bus_addr[i * 5 +: 5]),
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.wb_data_write(bus_data_write[i * 16 +: 16]),
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.wb_data_read(bus_data_read[i * 16 +: 16]),
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.link_status(link_status[i]),
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.receiving(receiving[i])
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);
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mii_elastic_buffer #(
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.BUF_SIZE(ELASTIC_BUF_SIZE)
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) buffer (
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.clk(clk_125),
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.tx_ce(rx_ce[i]),
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.tx_en(rx_dv[i]),
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.tx_er(rx_er[i]),
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.txd(rxd[i * 4 +: 4]),
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.rx_ce(buf_ce),
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.rx_dv(buf_dv[i]),
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.rx_er(buf_er[i]),
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.rxd(buf_data[i * 4 +: 4])
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);
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end endgenerate
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reg buf_ce_next;
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reg [3:0] tx_counter, tx_counter_next;
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initial begin
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buf_ce = 0;
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tx_ce = 0;
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tx_counter = MII_100_RATIO - 1;
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end
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always @(*) begin
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buf_ce_next = 0;
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tx_counter_next = tx_counter - 1;
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if (!tx_counter) begin
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tx_counter_next = MII_100_RATIO - 1;
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buf_ce_next = 1;
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end
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end
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always @(posedge clk_125) begin
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buf_ce <= buf_ce_next;
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tx_ce <= buf_ce;
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tx_counter <= tx_counter_next;
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if (tx_ce) begin
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collision <= collision_next;
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transmitting <= transmitting_next;
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end
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end
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endmodule
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@ -0,0 +1,134 @@
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// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*
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* PHY with internal (unexposed) MII and a wishbone management interface
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*/
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`include "common.vh"
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`include "io.vh"
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module phy_internal (
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input clk_125,
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input clk_250,
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/* DP83223 */
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input indicate_data,
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input signal_detect,
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output request_data,
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/* MII */
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input mii_tx_ce,
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input mii_tx_en,
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input mii_tx_er,
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input [3:0] mii_txd,
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output mii_rx_ce,
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output mii_rx_dv,
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output mii_rx_er,
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output [3:0] mii_rxd,
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output mii_col,
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output mii_crs,
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/* Wishbone management */
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output wb_ack, wb_err,
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input wb_cyc, wb_stb, wb_we,
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input [4:0] wb_addr,
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input [15:0] wb_data_write,
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output [15:0] wb_data_read,
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/* Control/status */
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output link_status,
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output receiving,
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output false_carrier,
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output symbol_error
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);
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parameter WISHBONE = 1;
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parameter ENABLE_COUNTERS = 1;
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parameter [23:0] OUI = 0;
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parameter [5:0] MODEL = 0;
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parameter [3:0] REVISION = 0;
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wire isolate, tx_data, signal_status, link_monitor_test, descrambler_test;
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wire loopback, coltest;
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wire [1:0] rx_data, rx_data_valid;
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phy_core phy_core (
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.clk(clk_125),
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.tx_data(tx_data),
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.rx_data(rx_data),
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.rx_data_valid(rx_data_valid),
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.signal_status(signal_status),
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.tx_ce(mii_tx_ce),
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.tx_en(mii_tx_en),
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.txd(mii_txd),
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.tx_er(mii_tx_er),
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.rx_ce(mii_rx_ce),
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.rx_dv(mii_rx_dv),
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.rxd(mii_rxd),
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.rx_er(mii_rx_er),
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.crs(mii_crs),
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.col(mii_col),
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.loopback(loopback),
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.coltest(coltest),
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.link_monitor_test_mode(link_monitor_test),
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.descrambler_test_mode(descrambler_test),
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.link_status(link_status),
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.receiving(receiving),
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.false_carrier(false_carrier),
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.symbol_error(symbol_error)
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);
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pmd_dp83223 pmd (
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.clk_125(clk_125),
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.clk_250(clk_250),
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.signal_detect(signal_detect),
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.request_data(request_data),
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.indicate_data(indicate_data),
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.tx_data(tx_data),
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.rx_data(rx_data),
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.rx_data_valid(rx_data_valid),
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.signal_status(signal_status),
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.loopback(loopback)
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);
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generate if (WISHBONE) begin
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mdio_regs #(
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.OUI(OUI),
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.MODEL(MODEL),
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.REVISION(REVISION),
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.EMULATE_PULLUP(1'b1),
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.ENABLE_COUNTERS(ENABLE_COUNTERS)
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) mdio_regs (
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.clk(clk_125),
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.ack(wb_ack),
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.err(wb_err),
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.cyc(wb_cyc),
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.stb(wb_stb),
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.we(wb_we),
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.addr(wb_addr),
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.data_write(wb_data_write),
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.data_read(wb_data_read),
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.link_status(link_status),
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.negative_wraparound(!rx_data_valid),
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.positive_wraparound(rx_data_valid[1]),
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.false_carrier(false_carrier),
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.symbol_error(symbol_error),
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.loopback(loopback),
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.isolate(isolate),
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.coltest(coltest),
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.descrambler_test(descrambler_test),
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.link_monitor_test(link_monitor_test)
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);
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end else begin
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assign wb_ack = 0;
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assign wb_err = wb_cyc && wb_stb;
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assign loopback = 0;
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assign coltest = 0;
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assign descrambler_test = 0;
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assign link_monitor_test = 0;
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end endgenerate
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endmodule
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@ -0,0 +1,101 @@
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# SPDX-License-Identifier: AGPL-3.0-Only
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# Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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import itertools
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import cocotb
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from cocotb.binary import BinaryValue
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from cocotb.clock import Clock
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from cocotb.triggers import ClockCycles, Combine, FallingEdge, Join, RisingEdge, Timer
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from cocotb.types import LogicArray
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from .descramble import scramble
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from .mdio_regs import BMSR, BMSR_LSTATUS, VCR, VCR_LTEST, wb_xfer
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from .nrzi_encode import nrzi_encode
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from .nrzi_decode import nrzi_decode
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from .pcs_tx import as_nibbles, mii_send_packet, pcs_recv_packet
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from .pcs_rx import frame, mii_recv_packet
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from .scramble import descramble
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from .util import BIT, alist
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@cocotb.test(timeout_time=5, timeout_unit='us')
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async def test_hub(hub):
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hub.clk_125.value = BinaryValue('Z')
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hub.clk_250.value = BinaryValue('Z')
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hub.signal_detect.value = 0
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hub.wb_cyc.value = 1
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await Timer(1)
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await cocotb.start(Clock(hub.clk_125, 8, units='ns').start())
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await cocotb.start(Clock(hub.clk_250, 4, units='ns').start())
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wb = {
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'clk': hub.clk_125,
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'cyc': hub.wb_cyc,
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'stb': hub.wb_stb,
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'we': hub.wb_we,
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'addr': hub.wb_addr,
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'data_write': hub.wb_data_write,
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'data_read': hub.wb_data_read,
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'ack': hub.wb_ack,
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'err': hub.wb_err,
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}
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# Enable fast link stabilization for testing
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for i in range(4):
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await wb_xfer(wb, BIT(i + 5) + VCR, VCR_LTEST)
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packet = list(as_nibbles((0x55, *b"Hello world!")))
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packet_bits = list(itertools.chain.from_iterable(frame(packet)))
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itertools.chain(itertools.repeat(1, 120), packet_bits, itertools.repeat(1))
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async def send_rx(i, bits):
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hub.signal_detect[i].value = 1
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for bit in nrzi_encode(scramble(bits)):
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hub.indicate_data[i].value = bit
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await Timer(8, units='ns')
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hub.signal_detect[i].value = 0
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hub.indicate_data[i].value = BinaryValue('X')
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async def recv_tx(i, packets):
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async def bits():
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await ClockCycles(hub.clk_125, 1)
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while True:
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await RisingEdge(hub.clk_125)
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yield hub.request_data[i].value
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data = descramble(nrzi_decode(bits()))
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for expected, valid in packets:
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actual = await alist(pcs_recv_packet(None, data))
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if valid:
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assert actual == expected
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else:
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assert actual != expected
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await cocotb.start(send_rx(0, itertools.chain(
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itertools.repeat(1, 120),
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packet_bits,
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itertools.repeat(1, 120),
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packet_bits,
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itertools.repeat(1),
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)))
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await cocotb.start(send_rx(1, itertools.chain(
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itertools.repeat(1, 300),
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packet_bits,
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itertools.repeat(1),
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)))
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await cocotb.start(send_rx(2, itertools.repeat(1)))
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await cocotb.start(send_rx(3, itertools.repeat(1)))
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receivers = [
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await cocotb.start(recv_tx(0, ((packet, False),))),
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await cocotb.start(recv_tx(1, ((packet, True), (packet, False)))),
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await cocotb.start(recv_tx(2, ((packet, True), (packet, False)))),
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await cocotb.start(recv_tx(3, ((packet, True), (packet, False)))),
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]
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await Combine(*(Join(t) for t in receivers))
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for i in range(4):
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assert not await wb_xfer(wb, BIT(i + 5) + BMSR) & BMSR_LSTATUS
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assert await wb_xfer(wb, BIT(i + 5) + BMSR) & BMSR_LSTATUS
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