Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution ... (Oreilly 'Flex & Bison' page 189)		2017-09-30 06:39:07 +03:00
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.gitignore	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Makefile.inc	Adjust makefiles to work with out-of-tree builds	2015-08-12 15:04:44 +02:00
const2ast.cc	Fixed segfault on invalid verilog constant 1'b_	2015-09-22 08:13:09 +02:00
preproc.cc	Minor coding style fix	2017-09-26 13:50:14 +02:00
verilog_frontend.cc	Add a paragraph about pre-defined macros to read_verilog help message	2017-07-21 14:34:53 +02:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	Fix ignoring of simulation timings so that invalid module parameters cause syntax errors	2017-09-26 01:52:59 +02:00
verilog_parser.y	Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution	2017-09-30 06:39:07 +03:00