..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
QLF_TDP36K: truncation tests matter
2023-12-04 15:52:03 +01:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
Adding check for BLIF names command input plane size.
2022-08-21 23:18:20 -05:00
bram
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fmt
cxxrtl: reorganize runtime component files.
2023-11-28 15:32:36 +00:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
liberty
fix file rights
2023-05-17 13:39:57 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memlib
memory_libmap: look for ram_style attributes on surrounding signals
2023-10-19 19:23:35 +02:00
memories
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
opt
opt_expr: Fix 'signed X>=0' replacement for wide output ports
2023-08-01 13:50:12 +01:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
realmath
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
Proper example code
2022-03-14 15:39:11 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
sim
Replace GNU specific invocation of basename(1) with the equivalent
2022-10-23 11:02:18 +13:00
simple
test: add tests for `shiftadd` and `shiftmul`
2023-11-06 14:01:37 +01:00
simple_abc9
abc9: fix SCC issues ( #2694 )
2021-03-29 22:01:57 -07:00
smv
Progress in SMV back-end
2015-06-19 14:08:46 +02:00
sva
Fix sva_value_change_changed test for updated verific
2023-10-03 11:46:43 +02:00
svinterfaces
Resolve package types in interfaces ( #3658 )
2023-02-12 18:25:39 -05:00
svtypes
Corrected handling of nested typedefs of struct/union
2023-07-20 23:39:44 -04:00
techmap
booth: Extend test to catch bug from previous commit
2023-10-04 23:30:29 +02:00
tools
support file locations containing spaces
2022-08-08 20:30:50 +02:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
verific
verific: import attributes on ports
2023-10-20 18:31:41 +02:00
verilog
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
xprop
xprop tests: Make iverilog invocation more portable
2023-02-13 16:54:11 +01:00
gen-tests-makefile.sh
Out of bounds checking for struct/union members
2023-02-19 23:25:08 +01:00
497cd021af