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362 Commits

Author SHA1 Message Date
Clifford Wolf df9d096a7d Ignoring more system task and functions 2015-01-15 13:08:19 +01:00
Clifford Wolf a588a4a5c9 Fixed handling of "input foo; reg [0:0] foo;" 2015-01-15 12:53:12 +01:00
Clifford Wolf 8e8e791fb5 Consolidate "Blocking assignment to memory.." msgs for the same line 2015-01-15 12:41:52 +01:00
Fabio Utzig fff6f00b3c Enable bison to be customized 2015-01-08 09:56:20 -02:00
Clifford Wolf 1bd67d792e Define YOSYS and SYNTHESIS in preproc 2015-01-02 17:11:54 +01:00
Clifford Wolf eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf 0bb6b24c11 Added global yosys_celltypes 2014-12-29 14:30:33 +01:00
Clifford Wolf 90bc71dd90 dict/pool changes in ast 2014-12-29 03:11:50 +01:00
Clifford Wolf 137f35373f Changed more code to dict<> and pool<> 2014-12-28 19:24:24 +01:00
Clifford Wolf 7751c491fb Improved some warning messages 2014-12-27 03:40:27 +01:00
Clifford Wolf 12ca6538a4 Fixed mem2reg warning message 2014-12-27 03:26:30 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 1282a113da Fixed supply0/supply1 with many wires 2014-12-11 13:56:20 +01:00
Clifford Wolf 76c83283c4 Fixed minor bug in parsing delays 2014-11-24 14:48:07 +01:00
Clifford Wolf 56c7d1e266 Fixed two minor bugs in constant parsing 2014-11-24 14:39:24 +01:00
Clifford Wolf 87333f3ae2 Added warning for use of 'z' constants in HDL 2014-11-14 19:59:50 +01:00
Clifford Wolf 4e5350b409 Fixed parsing of nested verilog concatenation and replicate 2014-11-12 19:10:35 +01:00
Clifford Wolf fe829bdbdc Added log_warning() API 2014-11-09 10:44:23 +01:00
Clifford Wolf acf010d30d Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions 2014-11-08 11:38:44 +01:00
Clifford Wolf a21481b338 Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." 2014-10-30 14:01:02 +01:00
Clifford Wolf 37aa2e02db AST simplifier: optimize constant AST_CASE nodes before recursively descending 2014-10-29 08:29:51 +01:00
Clifford Wolf f9c096eeda Added support for task and function args in parentheses 2014-10-27 13:21:57 +01:00
Clifford Wolf c4a2b3c1e9 Improvements in $readmem[bh] implementation 2014-10-26 23:29:36 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 26cbe4a4e5 Fixed constant "cond ? string1 : string2" with strings of different size 2014-10-25 18:23:53 +02:00
Clifford Wolf c5eb5e56b8 Re-introduced Yosys::readsome() helper function 
(f.read() + f.gcount() made problems with lines > 16kB)
 2014-10-23 10:58:36 +02:00
Clifford Wolf 750c615e7f minor indenting corrections 2014-10-19 18:42:03 +02:00
Parviz Palangpour de8adb8ec5 Builds on Mac 10.9.2 with LLVM 3.5. 2014-10-19 11:14:43 -05:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
William Speirs 31267a1ae8 Header changes so it will compile on VS 2014-10-17 11:41:36 +02:00
William Speirs fda52f05f2 Wrapped math in int constructor 2014-10-17 11:28:14 +02:00
Clifford Wolf 3838856a9e Print "SystemVerilog" in "read_verilog -sv" log messages 2014-10-16 10:31:54 +02:00
Clifford Wolf 6b05a9e807 Fixed handling of invalid array access in mem2reg code 2014-10-16 00:44:23 +02:00
Clifford Wolf f65e1c309f Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Clifford Wolf c3e9922b5d Replaced readsome() with read() and gcount() 2014-10-15 01:12:53 +02:00
William Speirs fad0b0c506 Updated lexers & parsers to include prefixes 2014-10-15 00:48:19 +02:00
Clifford Wolf 0b9282a779 Added make_temp_{file,dir}() and remove_directory() APIs 2014-10-12 12:11:57 +02:00
Clifford Wolf b1596bc0e7 Added run_command() api to replace system() and popen() 2014-10-12 10:57:15 +02:00
Clifford Wolf 35fbc0b35f Do not the 'z' modifier in format string (another win32 fix) 2014-10-11 11:42:08 +02:00
Clifford Wolf 8263f6a74a Fixed win32 troubles with f.readsome() 2014-10-11 11:36:22 +02:00
Clifford Wolf 0a651f112f Disabled vhdl2verilog command for win32 builds 2014-10-11 10:46:19 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 48b00dccea Another $clog2 bugfix 2014-09-08 12:25:23 +02:00
Clifford Wolf 680eaaac41 Fixed $clog2 (off by one error) 2014-09-06 19:31:04 +02:00
Clifford Wolf deff416ea7 Fixed assignment of out-of bounds array element 2014-09-06 17:58:27 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00