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91 Commits

Author SHA1 Message Date
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 060bf4819a Small improvements in Verilog front-end docs 2016-05-20 16:21:35 +02:00
Clifford Wolf b8b39472bb Added manual download link to README 2016-05-09 12:43:49 +02:00
Wladimir J. van der Laan f9d7091c3b Add instructions for building manual on Ubuntu 2016-04-03 14:29:11 +02:00
Clifford Wolf 0db53284fd We have 2016 for a while now 2016-03-30 13:52:26 +02:00
Clifford Wolf fd3e10c295 Link to vlsitechnology.org for liberty files 2015-11-12 13:15:19 +01:00
Clifford Wolf f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf c89ceee219 Added $finish and $display to README 2015-09-18 10:01:08 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Larry Doolittle 6c00704a5e Another block of spelling fixes 
Smaller this time
 2015-08-14 23:27:05 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf 8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf 3fe18c26cd Added "keep_hierarchy" attribute 2015-02-25 12:46:00 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf ac7d5e0658 Auto-detect TCL version 2015-02-05 23:39:26 +01:00
Clifford Wolf a038787c9b Added onehot attribute 2015-02-04 18:52:54 +01:00
Clifford Wolf 3fe2441185 Minor README changes 2015-02-01 00:57:12 +01:00
Clifford Wolf b59bb8a528 Removed TODO list from README file 2015-02-01 00:48:22 +01:00
Clifford Wolf 9948ff2d8a Added yosys_banner(), Updated Copyright range 2015-02-01 00:39:59 +01:00
Clifford Wolf 81020269b2 README stuff 2015-01-20 20:59:50 +00:00
Clifford Wolf f7cf60b45c Removed psmisc from deps list (usually fuser is already installed and the package name for it varies) 2014-12-14 17:24:44 +01:00
Clifford Wolf cf55371a22 Added psmisc to prerequisites 2014-12-12 12:49:46 +01:00
Clifford Wolf 6c768c686f Added missing prerequisites to README 2014-12-12 11:34:25 +01:00
Clifford Wolf ac8f4d298b Improved nomem2reg documentation 2014-10-30 09:12:55 +01:00
Clifford Wolf 70b2efdb05 Added support for $readmemh/$readmemb 2014-10-26 20:33:10 +01:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf ee29ae2206 Removed yosys-svgviewer 2014-09-02 03:52:46 +02:00
Clifford Wolf 9f00a0cd2d Using "xdot" instead of "yosys-svgviewer" in show command 2014-09-02 03:28:46 +02:00
Clifford Wolf ba83a7bdc6 Added DPI-C documentation to README file 2014-08-22 14:37:14 +02:00
Clifford Wolf 74af3a2b70 Archibald Rust and Clifford Wolf: ffi-based dpi_call() 2014-08-22 14:22:09 +02:00
Clifford Wolf 640d9fc551 Added "via_celltype" attribute on task/func 2014-08-18 14:29:30 +02:00
Clifford Wolf f53984795d Added support for non-standard """ macro bodies 2014-08-13 13:03:38 +02:00
Clifford Wolf d259abbda2 Added AST_MULTIRANGE (arrays with more than 1 dimension) 2014-08-06 15:52:54 +02:00
Clifford Wolf b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax 2014-08-04 15:40:07 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 89c85cac41 Added links to some liberty files to README 2014-06-28 12:11:42 +02:00
Clifford Wolf b1b96d199f Added more calls to "hierarchy" to README file 2014-06-15 11:51:51 +02:00
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf 12a3c05229 Updated README 2014-04-18 10:19:46 +02:00
Clifford Wolf 94c1307c26 Added libs/minisat (copy of minisat git master) 2014-03-12 10:17:51 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf 078cecf9ea Updated todo items in README file 2014-02-05 01:59:30 +01:00
Clifford Wolf d06258f74f Added constant size expression support of sized constants 2014-02-01 13:50:23 +01:00
Clifford Wolf 1e2440e7ed Added note about SystemVerilog assert statement to README 2014-02-01 13:04:49 +01:00
Clifford Wolf aceab5fc08 Tiny change in example script in README 2014-01-29 11:11:10 +01:00
Clifford Wolf 09bd82db21 Fixes and other changes in README 2013-12-08 15:42:27 +01:00
Clifford Wolf 38e7fa6530 Tighter integration of ABC build 2013-11-27 09:08:35 +01:00