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Added $finish and $display to README

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Clifford Wolf 2015-09-18 10:01:08 +02:00
parent 7a230d3a8d
commit c89ceee219
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@ -367,6 +367,10 @@ Verilog Attributes and non-standard features
expressions as <size>. If the expression is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
- The system tasks $finish and $display are supported in initial blocks
in and unconditional context (only if/case statements on parameters
and constant values). The intended use for this is synthesis-time DRC.
Supported features from SystemVerilog
=====================================