whitequark
d5c07e5b6f
cxxrtl: track aliases in VCD writer.
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This commit changes the VCD writer such that for all signals that
share `debug_item.curr`, it would only emit a single VCD identifier,
and sample the value once.
Commit 9b39c6f7
added redundancy to debug information by including
alias wires, and increased the size of VCD files proportionally; this
commit eliminates the redundancy from VCD files so that their size
is the same as before.
2020-06-08 17:10:45 +00:00
whitequark
9b39c6f744
cxxrtl: emit debug information for alias wires.
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Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
2020-06-08 17:09:49 +00:00
clairexen
369dcb4e82
Merge pull request #2085 from rswarbrick/select
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Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
clairexen
0f209378a8
Merge pull request #2089 from rswarbrick/modports
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Simplify a modport check in hierarchy.cc
2020-06-08 15:48:11 +02:00
clairexen
fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
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Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
clairexen
f57524cf71
Merge pull request #2117 from PeterCrozier/struct_array
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Support packed arrays in struct/union.
2020-06-08 15:22:09 +02:00
clairexen
680913be85
Merge pull request #2119 from YosysHQ/mwk/fix-fsm-idstring
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fsm_extract: avoid calling log_signal to determine wire name
2020-06-08 15:18:32 +02:00
whitequark
a0466e1a96
cxxrtl: add missing installs of include files.
2020-06-08 12:55:11 +00:00
whitequark
8262997c4e
cxxrtl: fix typo in comment. NFC.
2020-06-08 12:50:35 +00:00
whitequark
fb3704c896
cxxrtl: minor debug-related improvements.
2020-06-08 12:50:35 +00:00
Marcelina Kościelnicka
28b9f49c94
fsm_extract: avoid calling log_signal to determine wire name
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log_signal can result in a string with spaces (when bit selection is
involved), which breaks the rule of IdString not containing whitespace.
Instead, remove the sigspec from the name entirely — given that the
resulting wire will have no users, it will be removed later anyway,
so its name doesn't really matter.
Fixes #2118
2020-06-08 03:49:58 +02:00
whitequark
210d129d9a
Merge pull request #2116 from whitequark/cxxrtl-vcd
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cxxrtl: add a VCD writer using debug information
2020-06-07 20:32:00 +00:00
Peter Crozier
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
whitequark
ff5500f11a
cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.
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To avoid confusion with the C++ source files that are a part of
the simulation itself and not a part of Yosys build.
2020-06-07 03:48:40 +00:00
whitequark
31f6c96b1f
cxxrtl: add a C API for writing VCD dumps.
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This C API is fully featured.
2020-06-07 03:48:00 +00:00
whitequark
68362a9053
cxxrtl: only write VCD values that were actually updated.
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On a representative design (Minerva SoC) this reduces VCD file size
by ~20× and runtime by ~3×.
2020-06-07 03:48:00 +00:00
whitequark
9c36102669
cxxrtl: add a VCD writer using debug information.
2020-06-07 03:48:00 +00:00
whitequark
534be6670d
Merge pull request #2115 from whitequark/cxxrtl-introspection
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cxxrtl: add debug information to the C++ API, and add introspection via a new C API
2020-06-06 22:31:52 +00:00
whitequark
c399359ed6
cxxrtl: add a C API for driving and introspecting designs.
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Compared to the C++ API, the C API currently has two limitations:
1. Memories cannot be updated in a race-free way.
2. Black boxes cannot be implemented in C.
2020-06-06 21:12:55 +00:00
whitequark
f6e16e7f4c
cxxrtl: generate debug information for non-localized public wires.
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Debug information describes values, wires, and memories with a simple
C-compatible layout. It can be emitted on demand into a map, which
has no runtime cost when it is unused, and allows late bound designs.
The `hdlname` attribute is used as the lookup key such that original
names, as emitted by the frontend, can be used for debugging and
introspection.
2020-06-06 21:12:55 +00:00
whitequark
784bfec67c
Merge pull request #2110 from BracketMaster/master
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MacOS has even stricter stack limits in catalina.
2020-06-06 12:23:06 +00:00
whitequark
bd2ecc2dd3
Merge pull request #2113 from whitequark/cxxrtl-fix-sshr
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cxxrtl: fix implementation of $sshr cell
2020-06-05 10:24:25 +00:00
N. Engelhardt
9669e0c7d5
Merge pull request #2109 from nakengelhardt/btor_internal_names
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btor backend: make not printing internal names default
2020-06-05 11:36:08 +02:00
whitequark
025663adff
cxxrtl: fix implementation of $sshr cell.
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Fixes #2111 .
2020-06-05 02:04:46 +00:00
Claire Wolf
7ad0c49905
Add latch detection for use_case_method in part-select write, fixes #2040
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:25:59 +02:00
Yehowshua Immanuel
da0778350b
more reasonable numbers for memory
2020-06-04 17:00:04 -04:00
Claire Wolf
7112f187cd
Add missing .gitignore file
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 22:25:47 +02:00
Yehowshua Immanuel
5d29a9f633
MacOS has even stricter stack limits in catalina.
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Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
2020-06-04 14:01:56 -04:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
clairexen
ba99c0ea81
Merge pull request #2099 from Xiretza/manual-include-path
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Use in-tree include directory in manual build
2020-06-04 18:23:33 +02:00
N. Engelhardt
d8d8deeaf4
Add codeowners file ( #2098 )
2020-06-04 18:20:08 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
N. Engelhardt
82798ae575
btor backend: make not printing internal names default
2020-06-04 16:24:16 +02:00
Claire Wolf
5e8a9c61cd
Add printf format attributes to btorf/infof helper functions
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 15:53:28 +02:00
clairexen
8efe6ee7f5
Merge pull request #2108 from nakengelhardt/btor_internal_names
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btor backend: add option to not include internal names
2020-06-04 15:48:40 +02:00
whitequark
5a5a9b4ffe
flatten: clean up log messages.
2020-06-04 12:22:59 +00:00
whitequark
d731fe054b
flatten: topologically sort modules.
2020-06-04 12:22:59 +00:00
N. Engelhardt
8ceb6686e0
btor backend: add option to not include internal names
2020-06-04 14:00:52 +02:00
whitequark
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
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Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
N. Engelhardt
44f1e65155
Merge pull request #2070 from hackfin/master
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Pyosys API: idict type handling
2020-06-04 11:17:08 +02:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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abc9: fixes around handling combinatorial loops
2020-06-03 17:35:46 -07:00
whitequark
6268bdfe6f
flatten: simplify.
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`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
2020-06-04 00:02:12 +00:00
whitequark
d3e2100306
flatten: simplify. NFC.
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Remove redundant sigmaps.
2020-06-04 00:02:12 +00:00
whitequark
66255dab4e
flatten: simplify.
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Flattening does not benefit from topologically sorting cells within
a module when processing them.
2020-06-04 00:02:12 +00:00
whitequark
5d2b6d1394
flatten: simplify. NFC.
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Flatten is non-recursive and doesn't need to keep track of handled
cells.
2020-06-04 00:02:12 +00:00
whitequark
3c3fa774e5
flatten: simplify. NFC.
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Flattening always does "non-recursive" mapping.
2020-06-04 00:02:12 +00:00
whitequark
e561a3a76f
flatten: simplify. NFC.
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The `celltypeMap` always maps `x` to `{x}`.
2020-06-04 00:02:12 +00:00
whitequark
6783876807
flatten: simplify. NFC.
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The `design` and `map` designs are always the same when flattening.
2020-06-04 00:02:12 +00:00
whitequark
9338ff66b9
RTLIL: factor out RTLIL::Module::addMemory. NFC.
2020-06-04 00:02:12 +00:00
whitequark
ebbbe2156e
flatten: rename techmap-related stuff. NFC.
2020-06-04 00:02:12 +00:00