Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Eddie Hung
e3d898dccb
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 13:44:08 -07:00
Eddie Hung
71eff6f0de
RTLIL::S{0,1} -> State::S{0,1} for headers
2019-08-07 11:14:03 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
234fcf1724
Fix typos
2019-08-06 19:07:45 -07:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
84f52aee0d
Add SigSpec::extract_end() convenience function
2019-08-06 15:25:11 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Eddie Hung
ed303b07b7
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 12:02:16 -07:00
Eddie Hung
84c7a562e5
Helper: SigSpec::operator[] to accept negative indices
2019-07-31 12:18:03 -07:00
Jakob Wenzel
70882a8070
replaced std::iterator with using statements
2019-07-25 09:51:09 +02:00
Jakob Wenzel
25685a9a5b
made ObjectIterator extend std::iterator
...
this makes it possible to use std algorithms on them
2019-07-24 16:35:40 +02:00
Eddie Hung
e87916b7eb
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
2019-07-19 14:03:34 -07:00
Eddie Hung
54708dfbd7
Add an SigSpec::at(offset, defval) convenience method
2019-07-19 13:54:57 -07:00
Eddie Hung
d63f105708
SigSpec::remove_const() to return SigSpec&
2019-07-17 10:44:11 -07:00
Eddie Hung
b29f26f6c7
SigSpec::extend_u0() to return *this
2019-07-15 16:23:12 -07:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
...
The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Eddie Hung
fb30fcb7c5
Undo iterator based Module::remove() for cells, as containers will not
...
invalidate
2019-06-27 15:03:21 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Clifford Wolf
ba2185ead8
Refactor hierarchy wand/wor handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
Clifford Wolf
287de4b848
Add rewrite_sigspecs2, Improve remove() wires
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00
Clifford Wolf
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
...
Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
...
Feature/python bindings
2019-04-22 14:47:52 +02:00
Eddie Hung
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
Clifford Wolf
5b915f0153
Add "wbflip" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
Eddie Hung
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
Eddie Hung
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
dfb242c905
Add "read_ilang -lib"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
Benedikt Tutzer
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
Clifford Wolf
3b796c033c
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
Clifford Wolf
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Eddie Hung
3ea0161ae7
Add IdString::ends_with()
2019-02-26 12:04:16 -08:00
whitequark
18291c20d2
proc_clean: remove any empty cases if all cases use all-def compare.
2018-12-23 09:04:30 +00:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
...
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Benedikt Tutzer
29efc9d0b1
Deleted duplicate Destructor
2018-08-21 11:07:59 +02:00
Benedikt Tutzer
95d65971f3
added some checks if python is enabled to make sure everything compiles if python is disabled in the makefile
2018-08-20 16:04:43 +02:00
Benedikt Tutzer
bf7b73acfc
Added Wrappers for:
...
-IdString
-Const
-CaseRule
-SwitchRule
-SyncRule
-Process
-SigChunk
-SigBit
-SigSpec
With all their member functions as well as the remaining member
functions for Cell, Wire, Module and Design and static functions of
rtlil.h
2018-08-13 15:18:46 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Benedikt Tutzer
e7d3f3cd46
added destructors for wires and cells
2018-07-10 08:52:36 +02:00
Benedikt Tutzer
8ebaeecd83
multiple designs can now exist independent from each other. Cells/Wires/Modules can now move to a different parent without referencing issues
2018-07-09 15:48:06 +02:00