Lofty
32082477b5
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 `dffs` test
...
Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Martin Povišer
4506e11d0f
booth: Extend test to catch bug from previous commit
2023-10-04 23:30:29 +02:00
Jannis Harder
c174597014
Fix sva_value_change_changed test for updated verific
2023-10-03 11:46:43 +02:00
Martin Povišer
b0045300fd
booth: Cut down the test
...
Cut the test down from taking ~25 s to ~3 s.
2023-09-28 11:55:51 +02:00
Martin Povišer
c4762d930e
Merge pull request #3930 from povik/verific-test-memsemantics
...
verific: Add test of accurate semantics in memory inference
2023-09-20 11:46:42 +02:00
Martin Povišer
99a5773911
Merge pull request #3920 from zachjs/asgn-expr
...
sv: support assignments within expressions
2023-09-20 11:30:14 +02:00
Zachary Snow
28e99f2b8c
fix width of post-increment/decrement expressions
2023-09-18 23:46:06 -04:00
Zachary Snow
7d07615dee
allow attributes in front of ++/-- statements
2023-09-18 23:46:02 -04:00
Martin Povišer
8222121164
verific: Add test of accurate semantics in memory inference
2023-09-18 16:37:15 +02:00
andyfox-rushc
6d29dc659b
renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script
2023-09-08 15:34:56 -07:00
Martin Povišer
25a33d4082
techmap: Make the Booth test deterministic
2023-09-07 14:56:56 +02:00
Martin Povišer
0c2a99ca47
techmap: Test the Booth multiplier
2023-09-07 14:46:59 +02:00
Zachary Snow
4edb1a1921
sv: support assignments within expressions
...
- Add support for assignments within expressions, e.g., `x[y++] = z;` or
`x = (y *= 2) - 1;`. The logic is handled entirely within the parser
by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
statements.
2023-09-05 22:27:55 -04:00
Miodrag Milanovic
a42c630264
put back previous test state, due to default change
2023-08-29 10:21:58 +02:00
Miodrag Milanovic
3b9ebfa672
Addressed code review comments
2023-08-25 11:10:20 +02:00
Miodrag Milanovic
ea50d96135
fixed tests
2023-08-23 10:54:29 +02:00
Asherah Connor
4a475fa7a2
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
Charlotte
860e3e4056
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
Charlotte
bf84861fc2
proc_clean: only consider fully-defined case operands.
2023-08-12 02:46:31 +02:00
Charlotte
ce245b5105
cxxrtl_backend: respect sync `$print` priority
...
We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs. We could probably move this grouping out of
the dump method.
2023-08-11 04:46:52 +02:00
Charlotte
04582f2fb7
verilog_backend: emit sync `$print` cells with same triggers together
...
Sort by PRIORITY, ensuring output order.
2023-08-11 04:46:52 +02:00
Charlotte
4ffdee65e0
cxxrtl: store comb $print cell last EN/ARGS in module
...
statics were obviously wrong -- may be multiple instantiations of any
given module. Extend test to cover this.
2023-08-11 04:46:52 +02:00
Charlotte
843ad9331b
cxxrtl: WIP: adjust comb display cells to only fire on change
...
Naming and use of statics to be possibly revised.
2023-08-11 04:46:52 +02:00
Charlotte
eb0fb4d662
tests: -std=c++11 not optional
2023-08-11 04:46:52 +02:00
Charlotte
992a728ec7
tests: CXX may be e.g. gcc, so use CC and link stdc++ explicitly
2023-08-11 04:46:52 +02:00
Charlotte
f9b149fa7b
cxxrtl: add "-print-output" option, test in fmt
2023-08-11 04:46:52 +02:00
Charlotte
a1de898fcc
fmt: merge fuzzers since we don't rely on BigInteger logic
...
This is per fmt's (effective) use, as it turns out, so we're not losing
any fidelity in the comparison.
2023-08-11 04:46:52 +02:00
Charlotte
3571bf2c2d
fmt: fuzz, remove some unnecessary busywork
...
Removing some signed checks and logic where we've already guaranteed the
values to be positive. Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
2023-08-11 04:46:52 +02:00
Charlotte
2ae551c0af
fmt: fuzz, fix (remove extraneous + incorrect fill)
...
"blk + chunks" is often an overrun, plus the fill is unnecessary; we
throw blk away immediately.
2023-08-11 04:46:52 +02:00
Charlotte
9f9561379b
fmt: format %t consistently at initial
2023-08-11 04:46:52 +02:00
Charlotte
75b44f21d1
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
Charlotte
c382d7d3ac
fmt: %t/$time support
2023-08-11 04:46:52 +02:00
Charlotte
b0f69f2cd5
tests: test cxxrtl against iverilog (and uncover bug!)
2023-08-11 04:46:52 +02:00
Charlotte
51d9b73107
fmt: tests completing again
...
We need to invoke "read_verilog" manually, since the default action on
input files is to defer processing. Under such conditions, we never
simplify the AST, and initial $prints never execute.
2023-08-11 04:46:52 +02:00
Charlotte
1eff84cb92
fmt: ensure test exits on fail
...
shebang not honoured when directly called with "bash run-test.sh".
2023-08-11 04:46:52 +02:00
whitequark
c285880684
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
whitequark
67052f62ec
fmt: add tests for Yosys evaluation of format expressions.
2023-08-11 04:46:52 +02:00
whitequark
9f8e039a4b
ast: use new format string helpers.
2023-08-11 04:46:52 +02:00
Martin Povišer
f8325f66b7
opt_expr: Fix 'signed X>=0' replacement for wide output ports
...
If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.
Fixes #3867 .
2023-08-01 13:50:12 +01:00
Martin Povišer
93988ef5df
tests: Extend aigmap.ys with SAT comparison
...
Extend the aigmap.ys test with SAT-based comparison of the original
cells and their AIG implementations.
This tests both the usual cells and the single-bit Yosys gates.
2023-07-31 16:26:50 +02:00
N. Engelhardt
43780c9812
Merge pull request #3838 from povik/various-cleanup
2023-07-24 16:24:23 +02:00
Dag Lem
cff53d6d87
Corrected handling of nested typedefs of struct/union
...
This also corrects shadowing of constants in struct/union types.
2023-07-20 23:39:44 -04:00
Martin Povišer
f0ae046c5a
opt_share: Fix input confusion with ANDNOT, ORNOT gates
...
Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.
Fixes #3848 .
2023-07-20 20:58:52 +01:00
Martin Povišer
7c6cc4c40b
tests: Fix invocation of 'help -cells'
...
There's no such thing as 'help -celltypes' and there probably never was.
2023-07-10 12:42:09 +02:00
Jannis Harder
a07f8ac38a
check: Also check for conflicts with constant drivers
2023-06-23 18:07:28 +02:00
Miodrag Milanovic
e6f7cf3b29
Update tests
2023-06-09 14:41:45 +02:00
Eddie Hung
862631d657
Add ABC9 DSP cascade test
2023-05-25 18:42:08 +01:00
Lofty
00b0e850db
intel_alm: re-enable carry chains for ABC9
2023-05-25 18:28:10 +01:00
CORRADI Quentin
e7156c644d
Standard compliance for tests/verilog/block_labels.ys
...
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
2023-05-21 16:38:14 -04:00