fmt: add tests for Verilog round trip of format expressions.

tests/fmt/.gitignore

@@ -1,2 +1,3 @@
 *.log
-iverilog-initial_display*
+iverilog-*
+yosys-*

tests/fmt/always_display.v

@@ -0,0 +1,17 @@
+module m(input clk, rst, en, input [31:0] data);
+
+`ifdef EVENT_CLK
+	always @(posedge clk)
+`endif
+`ifdef EVENT_CLK_RST
+	always @(posedge clk or negedge rst)
+`endif
+`ifdef EVENT_STAR
+	always @(*)
+`endif
+`ifdef COND_EN
+		if (en)
+`endif
+			$display("data=%d", data);
+
+endmodule

tests/fmt/roundtrip.v

@@ -0,0 +1,22 @@
+module m(input clk, input `SIGN [31:0] data);
+
+	always @(posedge clk)
+		// All on a single line to avoid order effects.
+`ifdef BASE_DEC
+		$display(":%d:%-d:%+d:%+-d:%0d:%-0d:%+0d:%+-0d:%20d:%-20d:%+20d:%+-20d:%020d:%-020d:%+020d:%+-020d:",
+		         data, data, data, data, data, data, data, data, data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_HEX
+		$display(":%h:%-h:%0h:%-0h:%20h:%-20h:%020h:%-020h:",
+		         data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_OCT
+		$display(":%o:%-o:%0o:%-0o:%20o:%-20o:%020o:%-020o:",
+		         data, data, data, data, data, data, data, data);
+`endif
+`ifdef BASE_BIN
+		$display(":%b:%-b:%0b:%-0b:%20b:%-20b:%020b:%-020b:",
+		         data, data, data, data, data, data, data, data);
+`endif
+
+endmodule

tests/fmt/roundtrip_tb.v

@@ -0,0 +1,13 @@
+module tb;
+	reg clk = 1'b0;
+	reg [31:0] data;
+
+	m dut(.clk(clk), .data(data));
+
+	initial begin
+		data = 32'haa;
+		#10; clk = 1; #10; clk = 0;
+		data = 32'haaaa;
+		#10; clk = 1; #10; clk = 0;
+	end
+endmodule

tests/fmt/run-test.sh

@@ -1,6 +1,46 @@
-#!/bin/bash -eu
+#!/bin/bash -ex
 
 ../../yosys initial_display.v | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >yosys-initial_display.log
 iverilog -o iverilog-initial_display initial_display.v
 ./iverilog-initial_display >iverilog-initial_display.log
 diff yosys-initial_display.log iverilog-initial_display.log
+
+test_always_display () {
+	local subtest=$1; shift
+	../../yosys $* always_display.v -p 'proc; opt_expr -mux_bool; clean' -o yosys-always_display-${subtest}-1.v
+	../../yosys yosys-always_display-${subtest}-1.v -p 'proc; opt_expr -mux_bool; clean' -o yosys-always_display-${subtest}-2.v
+	diff yosys-always_display-${subtest}-1.v yosys-always_display-${subtest}-2.v
+}
+
+test_always_display clk -DEVENT_CLK
+test_always_display clk_rst -DEVENT_CLK_RST
+test_always_display star -DEVENT_STAR
+
+test_always_display clk_en -DEVENT_CLK -DCOND_EN
+test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
+test_always_display star_en -DEVENT_STAR -DCOND_EN
+
+test_roundtrip () {
+	local subtest=$1; shift
+	../../yosys $* roundtrip.v -p 'proc; clean' -o yosys-roundtrip-${subtest}-1.v
+	../../yosys yosys-roundtrip-${subtest}-1.v -p 'proc; clean' -o yosys-roundtrip-${subtest}-2.v
+	diff yosys-roundtrip-${subtest}-1.v yosys-roundtrip-${subtest}-2.v
+
+	iverilog $* -o iverilog-roundtrip-${subtest} roundtrip.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest} >iverilog-roundtrip-${subtest}.log
+	iverilog $* -o iverilog-roundtrip-${subtest}-1 yosys-roundtrip-${subtest}-1.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-1.log
+	iverilog $* -o iverilog-roundtrip-${subtest}-2 yosys-roundtrip-${subtest}-2.v roundtrip_tb.v
+	./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-2.log
+	diff iverilog-roundtrip-${subtest}.log iverilog-roundtrip-${subtest}-1.log
+	diff iverilog-roundtrip-${subtest}-1.log iverilog-roundtrip-${subtest}-2.log
+}
+
+test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=""
+test_roundtrip dec_signed -DBASE_DEC -DSIGN="signed"
+test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip hex_signed -DBASE_HEX -DSIGN="signed"
+test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip oct_signed -DBASE_HEX -DSIGN="signed"
+test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=""
+test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed"