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2233 Commits

Author SHA1 Message Date
Miodrag Milanovic 6dc62bd013 Fix out of tree build 2023-12-06 09:56:35 +01:00
Miodrag Milanovic d71dd5b9bb Fix out of tree build 2023-12-06 09:11:51 +01:00
Martin Povišer 16ea497d7c pmgen: Have a single make pattern 
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
 2023-12-05 18:30:13 +01:00
Martin Povišer e0fc48e196 quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
Martin Povišer 22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
N. Engelhardt f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Martin Povišer e0a6a01ecb quicklogic: Add `RAM_INIT` to specialized BRAM models 2023-12-04 15:52:03 +01:00
Martin Povišer 4903f99f85 quicklogic: Add missing `RAM_INIT` param on TDP36K sim model 2023-12-04 15:52:03 +01:00
Martin Povišer b602c0858f quicklogic: Set initial values on inferred TDP36K 2023-12-04 15:52:03 +01:00
Martin Povišer b30544d61d ql_dsp_io_regs: Fix ID strings, constant detection 2023-12-04 15:52:03 +01:00
Martin Povišer dad85b5178 synth_quicklogic: Fix missing FF mapping 2023-12-04 15:52:03 +01:00
Martin Povišer 532aca28ab quicklogic: Drop `blackbox` off `adder_carry` 2023-12-04 15:52:03 +01:00
Martin Povišer e19833f8c7 synth_quiclogic: Fix conditioning of bram passes 2023-12-04 15:52:02 +01:00
Martin Povišer e43810e13f ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
Martin Povišer 7d738b07da ql_dsp_*: Clean up 
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
 2023-12-04 15:52:02 +01:00
Martin Povišer 4bb4fd358e ql_k6n10f: Remove support for parameter-configured DSP variety 2023-12-04 15:52:02 +01:00
N. Engelhardt b80b1ab8b6 merge brams_final_map.v into brams_map.v 2023-12-04 15:52:02 +01:00
N. Engelhardt 20d864bbde add dsp inference 2023-12-04 15:52:02 +01:00
N. Engelhardt 6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries 2023-12-04 15:52:02 +01:00
N. Engelhardt 48c1fdc33d add qlf_k6n10f architecture + bram inference 
(Copied from QuickLogic Yosys plugin repo)
 2023-12-04 15:52:02 +01:00
N. Engelhardt 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
gatecat bf955cc2b0 nexus: Fix format strings to remove space padding 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-03 10:36:34 +01:00
N. Engelhardt beaae79e73
Merge pull request #4021 from povik/booth-wallace 
Change `booth` architecture for improved delay, similar signed/unsigned results
 2023-11-27 16:26:03 +01:00
Martin Povišer de16cd253d synth_lattice: Enable `booth` by default on XO3 2023-11-22 15:47:11 +01:00
Lofty 5c96746309 ice40: fix -noabc9 2023-11-17 12:49:17 +00:00
Lofty 309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
N. Engelhardt 8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again 
ice40, ecp5, gowin: enable ABC9 by default
 2023-11-13 17:29:57 +01:00
N. Engelhardt 52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work 
MachXO3 QoR improvements
 2023-11-13 16:56:06 +01:00
N. Engelhardt 3fef81b537
Merge pull request #4028 from povik/cmp2softlogic 
synth_lattice: Optionally do constant comparisons in soft logic
 2023-11-13 16:53:04 +01:00
Lofty 7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
Martin Povišer 3ffa4b5e5d synth_lattice: Wire up `cmp2softlogic` as an option 2023-11-13 10:42:12 +01:00
Martin Povišer f7d4a855c6 techlibs: Add `cmp2softlogic.v` to common 2023-11-13 10:42:12 +01:00
Krystine Sherwin 83d2f4f334
techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
Martin Povišer fed2720999 synth_lattice: Optimize flip-flop memories better 
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
 2023-11-07 16:29:56 +01:00
Martin Povišer ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals 
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
 2023-11-07 16:21:39 +01:00
Lofty b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty 32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Lofty 294844137b gowin: fix abc9 attributes and specify blocks 2023-10-04 00:16:10 +01:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master 
multpass -- create Booth Encoded multipliers for
 2023-09-18 16:46:59 +02:00
Jannis Harder 78ff40d1b2 Run `future` as part of `prep` 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
andyfox-rushc 0fa412502c mult -> booth in synth.cc, to turn on use synth -booth 2023-09-08 16:44:59 -07:00
andyfox-rushc 1d92ea8001 Support for turning on mult pass from generic synth command 2023-09-08 16:16:24 -07:00
Miodrag Milanovic 72bec94ef4 Add missing file for XO3D 2023-09-01 10:15:51 +02:00
Miodrag Milanovic 792cf8326e defult nowidelut for xo2/3/3d 2023-08-29 10:08:55 +02:00
Miodrag Milanovic b168ff99d0 fix generated blackboxes for ecp5 2023-08-28 16:26:26 +02:00
Miodrag Milanovic 0756285710 enable more primitives supported with nextpnr 2023-08-25 11:45:25 +02:00
Miodrag Milanovic 3b9ebfa672 Addressed code review comments 2023-08-25 11:10:20 +02:00
Miodrag Milanovic 541c1ab567 add script for blackbox extraction 2023-08-23 11:51:00 +02:00