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3806 Commits

Author SHA1 Message Date
Jannis Harder dda972a148 sim: New -append option for Yosys witness cosim 
This is needed to support SBY's append option.
 2023-01-11 18:07:16 +01:00
Jannis Harder 2dd5652215 sim: Add Yosys witness (.yw) cosimulation 2023-01-11 18:07:16 +01:00
Jannis Harder f6458bab70 sim: Only check formal cells during gclk simulation updates 
This is required for compatibility with non-multiclock formal semantics.
 2023-01-11 18:07:16 +01:00
Jannis Harder 9c6198a827 sim: Internal API to set $initstate 
This is not yet added to any of the simulation drivers.
 2023-01-11 18:07:16 +01:00
Jannis Harder 44b26d5c6d sim: Emit used memory addresses as signals to output traces 
This matches the behavior of smtbmc.

This also updates the sim internal memory API to allow masked writes
where State::Sa bits (internal don't care - not a valid value for a
signal) leave the memory content unchanged.
 2023-01-11 18:07:16 +01:00
Jannis Harder 5042600c0d xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundef 
This adds the xprop_decoder attribute to bwmuxes that drive the original
unencoded signals. Setundef is changed to ignore the x inputs of these
bwmuxes, so that they survive the prep script of SBY's formal flow. This
is required to make simulation (via sim) using the prep model show the
decoded x signals instead of 0/1 values made up by the solver.
 2023-01-11 18:07:16 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
Miodrag Milanovic e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output 
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
 2022-12-29 21:51:46 -05:00
Claire Xenia Wolf 029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-21 14:50:23 +01:00
Claire Xenia Wolf 1bc832a8e1 Allow non-unique modules without state in sim writeback-mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:43:02 +01:00
Claire Xenia Wolf a9072dc23c Small bugfix in uniquify pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:41:48 +01:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code 
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
 2022-12-12 17:51:01 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-09 18:28:17 +01:00
Jannis Harder 967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode 2022-12-09 15:25:40 +01:00
Claire Xenia Wolf dc14def5f3 Add gold-x handing to miter cross port handling 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-08 22:14:16 +01:00
Claire Xenia Wolf 3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00
Jannis Harder 172a8e79f0 xprop: Add -split-public option 2022-12-08 20:00:01 +01:00
Claire Xenia Wolf 068031d2aa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 16:10:58 +01:00
Claire Xenia Wolf aeba966475 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 12:46:49 +01:00
Claire Xenia Wolf c679b408cb Various improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:43:01 +01:00
Claire Xenia Wolf 2895a66784 Bugfix in splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:00:48 +01:00
Claire Xenia Wolf e151e44caa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 19:32:31 +01:00
Claire Xenia Wolf c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 11:35:10 +01:00
Claire Xenia Wolf 92fc6cd4a9 Add splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 01:33:04 +01:00
Jannis Harder 7036a312bf stat: Fix JSON output for empty designs 2022-12-02 14:36:19 +01:00
Jannis Harder ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Claire Xenia Wolf 956b7f5fd1 Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff 2022-12-01 11:31:39 +01:00
Claire Xenia Wolf fbf8bcf38f Add insbuf -chain mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-01 10:02:35 +01:00
Jannis Harder eb0039848b miter: Add -make_cover option to cover each output pair difference 2022-11-30 19:01:28 +01:00
Jannis Harder 551ca7f97f formalff: Fix -ff2anyinit assertion error for fine FFs 2022-11-30 19:01:28 +01:00
Jannis Harder ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic 2022-11-30 19:01:28 +01:00
Jannis Harder 5ff69a0fe2 sim: Improved global clock handling 2022-11-30 18:50:53 +01:00
Jannis Harder 3ecf85e32c opt_expr: Optimizations for `$bweqx` and `$bwmux` 2022-11-30 18:50:53 +01:00
Jannis Harder be752a20dc Add bwmuxmap pass 2022-11-30 18:50:53 +01:00
Jannis Harder 7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells 
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
 2022-11-30 18:24:35 +01:00
Jannis Harder 1e67c3a3c2 opt_expr: Fix shift/shiftx optimizations 2022-11-30 18:24:25 +01:00
Jannis Harder fd56d1f79e opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cells 2022-11-29 19:06:45 +01:00
Jannis Harder c08242ba41 opt_expr: Optimize bitwise logic ops with one fully const input 2022-11-29 19:06:45 +01:00
Jannis Harder 661fa5ff92 simplemap: Map `$xnor` to `$_XNOR_` cells 
The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
 2022-11-29 19:06:45 +01:00
Jannis Harder ed0e14820e sat: Add -set-def-formal option to force defined $any* outputs 2022-11-28 14:50:52 +01:00
Miodrag Milanovic b0be19c126 Support importing verilog configurations using Verific 2022-11-25 13:02:11 +01:00
N. Engelhardt b64141f48b mention prerequisites in fsm_detect and fsm help 2022-11-21 16:07:23 +01:00
KrystalDelusion a14dec79eb
Rst docs conversion (#3496) 
Rst docs conversion
 2022-11-15 12:55:22 +01:00
Jannis Harder 9b4fba3870 sim: Run a comb-only update step to set past values during FST cosim 
The previous approach only initialized past_d and past_ad while for FST
cosim we also need to initialize the other past values like past_clk,
etc. Also to properly initialize them, we need to run a combinational
update step in case any of the wires feeding into the FF are private or
otherwise not part of the FST.
 2022-11-07 14:09:33 +01:00
Claire Xenia Wolf a4eb7e41c0 Add extra time at the end of a sat VCD trace 
Otherwise the final values will not show up in gtkwave waveforms
when looking at the generated traces.

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-11-01 17:51:46 +01:00