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1932 Commits

Author SHA1 Message Date
Clifford Wolf 50ac284823 Fixes in $alu SAT- and eval-models 2014-09-03 13:39:46 +02:00
Clifford Wolf 635b922afe Undef-related fixes in simlib $alu model 2014-09-02 23:21:59 +02:00
Clifford Wolf f1869667ca Improvements in "test_cell -vlog" 2014-09-02 23:21:15 +02:00
Clifford Wolf 66bf2bb92e Added test_cell -vlog 2014-09-02 22:49:43 +02:00
Clifford Wolf da360771a1 Create a default selection stack in RTLIL::Design::Design() 2014-09-02 22:49:24 +02:00
Clifford Wolf c38283dbd0 Small bug fixes in $not, $neg, and $shiftx models 2014-09-02 17:48:41 +02:00
Clifford Wolf acd7a99aef Added SAT testing to test_cell eval stage 2014-09-02 17:28:13 +02:00
Ahmed Irfan 2446b6fbef added $pmux cell translation 2014-09-02 14:47:51 +02:00
Clifford Wolf 37fe7c7bdf Removed references to yosys-svgviewer from docs 2014-09-02 04:03:06 +02:00
Clifford Wolf ee29ae2206 Removed yosys-svgviewer 2014-09-02 03:52:46 +02:00
Clifford Wolf 9f00a0cd2d Using "xdot" instead of "yosys-svgviewer" in show command 2014-09-02 03:28:46 +02:00
Clifford Wolf 630befdf6d Added $alu support to test_cell 2014-09-01 16:36:04 +02:00
Clifford Wolf 2fcf66b91d Added ConstEval model for $alu cells 2014-09-01 16:35:46 +02:00
Clifford Wolf bae09dca2b Added SAT model for $alu cells 2014-09-01 16:35:25 +02:00
Clifford Wolf 9923762461 Fixed "test_cell -simlib all" 2014-09-01 15:37:56 +02:00
Clifford Wolf c7f81e4e49 Added "test_cell -simlib -v" 2014-09-01 15:37:21 +02:00
Clifford Wolf 826fdb34d8 Added "techmap -autoproc" 2014-09-01 15:36:29 +02:00
Clifford Wolf 27a1bfbec6 Fixes in old SAT example.ys 2014-09-01 11:45:47 +02:00
Clifford Wolf d5148f2e01 Moved "share" and "wreduce" to passes/opt/ 2014-09-01 11:45:26 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf e3664066d5 Added eval testing to test_cell 2014-08-31 18:08:42 +02:00
Clifford Wolf 83ec3fa204 Fixed return size of const_*() eval functions 2014-08-31 18:08:26 +02:00
Clifford Wolf be44157c0f Added RTLIL::Const::size() 2014-08-31 18:07:48 +02:00
Clifford Wolf a1c7d4a8e2 Added eval model for $lut cells 2014-08-31 17:43:31 +02:00
Clifford Wolf 0b6769af3f Typo fixes in cell->*Param() API 2014-08-31 17:43:31 +02:00
Clifford Wolf 8649b57b6f Added $lut support in test_cell, techmap, satgen 2014-08-31 17:43:31 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf 88db09255b Added autotest -e (do not use -noexpr on write_verilog) 2014-08-30 18:34:07 +02:00
Clifford Wolf 6ff46323a3 Improved write address decoder generation memory_map 2014-08-30 18:18:15 +02:00
Clifford Wolf dfbd7dd15a Fixed module->addPmux() 2014-08-30 18:17:22 +02:00
Clifford Wolf 66763fad4e Using worker class in memory_map 2014-08-30 17:39:08 +02:00
Clifford Wolf eb571cba6a Replaced $__alu CO/CS outputs with full-width CO output 2014-08-30 15:12:39 +02:00
Clifford Wolf 3a7d5d188d Don't change existing binary FSM encoding if it is already optimal 2014-08-30 14:43:06 +02:00
Clifford Wolf f910481f35 Using $pmux info in fsm_extract to optimize transition ctrl_in patterns 2014-08-30 14:34:49 +02:00
Clifford Wolf ab019b0bd5 Improved handling of $pmux cells in fsm_extract 2014-08-30 14:11:57 +02:00
Clifford Wolf d148b0af0d Fixed inserting of Q-inverters in dfflibmap 2014-08-27 19:44:12 +02:00
Clifford Wolf cfb4338319 Fixed printing of multi-line Makefile.conf 2014-08-27 12:13:53 +02:00
Clifford Wolf 084685f480 Implemented "rename -enumerate -pattern" 2014-08-26 12:51:08 +02:00
Clifford Wolf e70480655e Print Makefile.conf as make info message 2014-08-26 10:11:46 +02:00
Clifford Wolf 672b2c6db1 Checking for valid CONFIG value in Makefile 2014-08-25 12:48:20 +02:00
Clifford Wolf 7bbbe3580d Optimize shift ops with constant rhs in opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf 641501203c Added some additional log messages to opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf eda603105e Added is_signed argument to SigSpec.as_int() and Const.as_int() 2014-08-24 15:14:00 +02:00
Clifford Wolf 9c5a63c52c azonenberg: Make dump_vcd save model when temporal induction fails due to step limit 2014-08-24 13:27:40 +02:00
Clifford Wolf c642dd0b3e Only call proc_share_dirname() in techmap when necessary 2014-08-23 15:32:00 +02:00
Clifford Wolf 58367cd87a Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore 2014-08-23 15:14:58 +02:00
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf fff12c719f Added "stat -width" 2014-08-22 17:20:28 +02:00