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5238 Commits

Author SHA1 Message Date
Clifford Wolf 6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00
Clifford Wolf 00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix 
initialize more registers in setundef -init
 2019-06-05 09:50:15 +02:00
Clifford Wolf 4190d7c094 Fix typo in fmcombine log message, fixes #1063 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:26:44 +02:00
Clifford Wolf 8a6f9977f6 Suppress driver-driver conflict warning for unknown cell types, fixes #1065 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:14:12 +02:00
Clifford Wolf dd3c333c0a Remove yosys_banner() from python wrapper init, fixes #1056 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 08:57:33 +02:00
Clifford Wolf 1332051f33
Merge pull request #1062 from tux3/patch-1 
README.md: Missing formatting for <tag>
 2019-06-04 14:37:10 +02:00
Tux3 c66d644b66
README.md: Missing formatting for <tag> 2019-06-04 10:45:41 +02:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung 1217e47e83
Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map 
Execute techmap and arith_map simultaneously
 2019-06-03 20:23:37 -07:00
Eddie Hung 02973474df Remove extra newline 2019-06-03 20:04:47 -07:00
Eddie Hung 0ad50332d9 Execute techmap and arith_map simultaneously 2019-06-03 19:36:09 -07:00
Maciej Kurc 5739cf5265 Added tests for attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-03 09:25:20 +02:00
Clifford Wolf 36120fcc30 Only support Symbiotic EDA flavored Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-02 10:14:50 +02:00
Maciej Kurc a6cadf6318 Added support for parsing attributes on port connections. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-31 14:58:43 +02:00
Clifford Wolf 90ec2cda42 Fix "tee" handling of log_streams 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-31 09:28:51 +02:00
Clifford Wolf 2faa1d0e80 Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-30 10:04:26 +02:00
Clifford Wolf 0df8a3b461
Merge pull request #1057 from mmicko/fix_478 
Aded one more load of .conf to support change of prefix
 2019-05-30 09:58:51 +02:00
Miodrag Milanovic 14bd40cd3d Aded one more load of .conf to support change of prefix 2019-05-29 18:57:03 +02:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047 
Do not use shiftmul peepopt pattern when mul result is truncated
 2019-05-28 19:02:26 +02:00
Clifford Wolf 8e647901ef
Merge pull request #1050 from YosysHQ/clifford/wandwor 
Refactored wand/wor support
 2019-05-28 17:42:16 +02:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 17:17:56 +02:00
Clifford Wolf 49d641d97f
Merge pull request #1048 from mmicko/fix_enable_pyosys 
Moved pyosys block in Makefile
 2019-05-28 16:52:40 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Clifford Wolf e3ebac44df Add actual wandwor test that is part of "make test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:42:50 +02:00
Clifford Wolf eaae0adf57 Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor 2019-05-28 15:45:15 +02:00
Miodrag Milanovic 040b06cb37 Remove info line in 2nd load of conf file 2019-05-28 15:43:27 +02:00
Miodrag Milanovic 1575d962fa Moved pyosys block in Makefile 2019-05-28 14:53:07 +02:00
Clifford Wolf 2a11c48782
Merge pull request #1045 from mmicko/afl-gcc-target 
afl-fuzzer compile config
 2019-05-28 14:00:28 +02:00
Miodrag Milanovic 1bbcd277fb make config-afl-gcc to help creating conf file 2019-05-27 20:43:10 +02:00
Miodrag Milanovic 2ccbfc8d38 Added afl-gcc as target for fuzzer 2019-05-27 20:38:44 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel f68b658b4b reformat wand/wor test 2019-05-27 18:45:54 +02:00
Stefan Biereigel c5fe04acfd remove port direction workaround from test case 2019-05-27 18:10:39 +02:00
Stefan Biereigel 7f11a73210 update README.md with wand/wor information 2019-05-27 18:07:12 +02:00
Stefan Biereigel cd12f2ddcf remove leftovers from ast data structures 2019-05-27 18:01:44 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf 92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range 
Give error instead of asserting for invalid range, fixes #947
 2019-05-27 13:26:12 +02:00
Clifford Wolf 40a070e269
Merge pull request #1043 from mmicko/unsized_constant 
Added support for unsized constants, fixes #1022
 2019-05-27 13:25:52 +02:00
Clifford Wolf 2a9c68e2d6
Merge pull request #1026 from YosysHQ/clifford/fix1023 
Keep zero-width wires in opt_clean if and only if they are ports
 2019-05-27 13:24:19 +02:00
Clifford Wolf da140dd260
Merge pull request #1030 from Kmanfi/makefile_osx 
OS X related Makefile fixes.
 2019-05-27 13:22:51 +02:00
Miodrag Milanovic 84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic 34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Kaj Tuomi 90d070d294 Guard all Python-api related items. 2019-05-27 11:31:50 +03:00
Clifford Wolf 2058c7c53b
Merge pull request #1035 from YosysHQ/eddie/opt_rmdff 
opt_rmdff to work on $dffe and $_DFFE_*
 2019-05-26 11:44:31 +02:00
Clifford Wolf ba92721613
Merge pull request #1042 from mmicko/git_ignore_python 
Add files to ignore for python build
 2019-05-26 10:40:40 +02:00
Miodrag Milanovic ece551eaff Add files to ignore for python build 2019-05-26 09:31:43 +02:00
Eddie Hung d4fb6cac7c Revert enable check 2019-05-25 12:55:57 -07:00
Clifford Wolf a90eec12c9
Merge pull request #1041 from YosysHQ/clifford/fix1040 
Fix handling of offset and upto module ports in write_blif
 2019-05-25 19:17:05 +02:00
Clifford Wolf 6352df42ae Fix handling of offset and upto module ports in write_blif, fixes #1040 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-25 17:45:14 +02:00
Eddie Hung f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00