Commit Graph

4052 Commits

Author SHA1 Message Date
Emil J c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning
opt_demorgan: fix extra args warning
2024-04-10 12:49:14 +02:00
Martin Povišer 47931f9050
Merge pull request #4295 from gadfort/add-ports-stat
add port statistics to stat command
2024-04-08 11:12:02 +02:00
Emil J. Tywoniak 4bb3b099d2 opt_demorgan: fix extra args warning 2024-04-03 10:02:53 +02:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Peter Gadfort 160e3e089a add port statistics to stat command 2024-03-22 09:20:20 -04:00
N. Engelhardt e4f11eb0a0
Merge pull request #4228 from povik/synth-inject
synth: Introduce `-extra-map` for amending techmap
2024-03-11 14:55:45 +01:00
Martin Povišer 206d894c56 check: Omit private wires in loop report 2024-03-11 10:45:36 +01:00
Martin Povišer d01728aaa5 celledges: Register async FF paths 2024-03-11 10:45:36 +01:00
Martin Povišer 4fdcf388d3 check: Assert edges data is not out-of-bounds 2024-03-11 10:45:17 +01:00
Martin Povišer b6112b3551 check: Consider read ports in loop detection 2024-03-11 10:45:17 +01:00
Martin Povišer fa74d0bd1a check: Use cell edges data in detecting combinational loops 2024-03-11 10:43:49 +01:00
Martin Povišer c5ae74af34 check: Improve found loop logging
Print the detected loop in-order, and include source location for each
node, if available.
2024-03-11 10:43:49 +01:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
celledges: support shift ops
2024-03-08 09:35:47 +01:00
Jannis Harder 04ecabdd1f
Merge pull request #4222 from jix/pdr-X
write_aiger: Include `$assert` and `$assume` cells in -ywmap output
2024-03-05 15:13:51 +01:00
Jannis Harder d8cdc213a6 rename -witness: Bug fix and rename formal cells
Rename formal cells in addition to witness signals. This is required to
reliably track individual property states for the non-smtbmc flows.

Also removes a misplced `break` which resulted in only partial witness
renaming.
2024-03-04 16:53:03 +01:00
Jannis Harder 16f6386613
Merge pull request #4224 from povik/equiv_simple-fix
equiv_simple: Take FFs into account for driver map
2024-03-04 15:53:34 +01:00
N. Engelhardt 6dc5da3ed9
Merge pull request #4232 from povik/mem-ui-fixes
opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-26 16:09:27 +01:00
Roland Coeurjoly 4a2fb18718 Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc 2024-02-25 17:23:56 +01:00
Roland Coeurjoly 033fa10307 We use CXX instead of LD for linking yosys-filterlib 2024-02-25 16:49:28 +01:00
Martin Povišer 030d639201 opt_mem, memory_*: Refuse to operate in presence of processes
Processes can contain `MemWriteAction` entries which are invisible to
most passes operating on memories but which will be lowered to write
ports later on by `proc_memwr`. For that reason we can get corrupted
RTLIL if we sequence the memory passes before `proc`. Address that by
making the affected memory passes ignore modules with processes.
2024-02-23 12:27:53 +01:00
Martin Povišer 975517b022 memory_memx: Fix log header 2024-02-23 12:27:10 +01:00
Martin Povišer 53ca7b48f8 techmap: Fix help message wording 2024-02-22 22:00:56 +01:00
Martin Povišer 4c96546717 equiv_simple: Take FFs into account for driver map
This fixes an issue introduced in commit 26644ea due to which flip-flops
are inadvertently ignored when building up driver map. The mentioned
commit wasn't without functional change after all.
2024-02-21 12:05:52 +01:00
Austin Rovinski 03cadf6474 dfflibmap: use patmatch() from kernel/yosys.cc
Replace OS matching functions with yosys kernel function

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-20 11:04:55 -05:00
Miodrag Milanović bc8a3a5b18
Merge pull request #4219 from rovinski/master
dfflibmap: Add a -dont_use flag to ignore cells
2024-02-20 12:43:44 +01:00
Miodrag Milanović a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href
show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-19 20:50:53 +01:00
Austin Rovinski 5059bb1d4f dfflibmap: force PathMatchSpecA on WIN32
Depending on the WIN32 compilation mode, PathMatchSpec may expect a LPCSTR or
LPCWSTR argument. char* is only convertable to LPCSTR, so use that
implementation

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 14:40:46 -05:00
Austin Rovinski 689feed012 dfflibmap: Add a -dont_use flag to ignore cells
This is an alternative to setting the dont_use property in lib. This brings
dfflibmap in parity with the abc pass for dont_use.

Signed-off-by: Austin Rovinski <rovinski@nyu.edu>
2024-02-19 13:00:18 -05:00
Martin Povišer db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
proc_rom: don't assert on big actionless switch.
2024-02-19 16:21:40 +01:00
N. Engelhardt 4b99db0b73
Merge pull request #4177 from povik/connect-extra_args
connect: Do interpret selection arguments
2024-02-19 15:18:37 +01:00
N. Engelhardt aebb7a0c4d
Merge pull request #4188 from povik/dlatch-bwmux
proc_dlatch: Include `$bwmux` among considered mux cells
2024-02-19 15:15:03 +01:00
Amelia Cuss bf4a46ccb3 proc_rom: don't assert on big actionless switch.
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
2024-02-18 01:33:28 +11:00
N. Engelhardt 61b3b9b58a
Merge pull request #4197 from QuantamHD/sequential_area
stat: Add sequential area output to stat -liberty
2024-02-16 19:15:44 +01:00
Ethan Mahintorabi b8a1009de9
Update passes/cmds/stat.cc
Make reporting line more clear about the non cumulative area of sequential cells

Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
2024-02-16 07:44:09 -08:00
Ethan Mahintorabi f0df0e3912
update type and variable names
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-16 00:01:44 +00:00
Ethan Mahintorabi 2d8343d423
update type and variable names
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-15 23:59:19 +00:00
Jannis Harder bbdfcfdf30 clk2fflogic: Fix handling of $check cells
Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
2024-02-14 11:42:27 +01:00
Miodrag Milanovic 834276a2f7 show: Add option to add cell/wire "src" attribute into graphviz attribute href 2024-02-14 09:50:53 +01:00
Miodrag Milanović edb95c69a9
Merge pull request #4084 from jix/scopeinfo
$scopeinfo support
2024-02-12 09:51:22 +01:00
Ethan Mahintorabi 8566489d85
stat: Add sequential area output to stat -liberty
Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.

```
   Chip area for module '\addr': 92.280720
   Sequential area for module '\addr': 38.814720
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-09 23:51:00 +00:00
Miodrag Milanović 2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix
ci: Fix CXXSTD typo
2024-02-08 18:55:47 +01:00
Martin Povišer 043f1e2bcb opt_lut: Remove leftover `-dlogic` help 2024-02-08 17:49:44 +01:00
Martin Povišer af1a5cfeb9 Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
Martin Povišer 862f2fd705 proc_dlatch: Include `$bwmux` among considered mux cells 2024-02-08 00:08:50 +01:00
Jannis Harder bfd9cf63db Ignore $scopeinfo in opt_merge 2024-02-06 17:51:29 +01:00
Jannis Harder 8902fc94b6 Suport $scopeinfo in flatten and opt_clean 2024-02-06 17:51:29 +01:00
Miodrag Milanović 269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 12:08:01 +01:00
Jannis Harder 0470cbb00d hierarchy: Without a known top module, derive all deferred modules
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00
Claire Xen 1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
N. Engelhardt f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean
opt_clean: Add commentary, remove dead code
2024-02-05 15:08:34 +01:00