riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,556 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

8556 Commits

Author SHA1 Message Date
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 2bda51ac34
Merge pull request #1639 from YosysHQ/eddie/fix_read_xaiger 
read_aiger: $lut prefix in front
 2020-01-15 16:22:49 -08:00
Eddie Hung 5918ede9bd abc9: aAdd test to check $_NOT_s are absorbed 2020-01-15 14:36:05 -08:00
Eddie Hung 05c8858a90 read_aiger: $lut prefix in front 2020-01-15 14:31:32 -08:00
Eddie Hung d6da9c0c0f write_xaiger: skip abc9_flop only if abc_box_seq present 2020-01-15 11:25:20 -08:00
Miodrag Milanović abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W 
synth_xilinx: fix default W value for non-xc7
 2020-01-15 08:47:16 +01:00
Eddie Hung 1c41dc6b95 write_xaiger: do not export flop inputs as POs 2020-01-14 16:17:27 -08:00
Eddie Hung 770e301b21 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 15:47:13 -08:00
Eddie Hung 4656f202c6 abc9_ops: -reintegrate to not trim box padding anymore 2020-01-14 14:27:29 -08:00
Eddie Hung ffd6f54f92
Merge pull request #1635 from YosysHQ/eddie/print_stats 
print_stats footer to return peak memory, option for including children
 2020-01-14 14:18:42 -08:00
Marcin Kościelnicki a5d2358a60 fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks. 
Fixes #1634.
 2020-01-14 22:49:20 +01:00
Eddie Hung 654247abe9 abc9_ops/write_xaiger: update doc 2020-01-14 12:40:36 -08:00
Eddie Hung 468386d67d abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger 2020-01-14 12:25:45 -08:00
Eddie Hung d21262ee04 Adding (* techmap_autopurge *) to FD* in abc9_map.v 2020-01-14 12:22:21 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung 61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung 9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630 
read_aiger: uniquify wires with $aiger<autoidx> prefix
 2020-01-14 11:40:40 -08:00
Eddie Hung ade57058f7 As before, only display MEM if Linux or FreeBSD 2020-01-14 11:38:48 -08:00
Eddie Hung 36d1a2c60f synth_xilinx: fix default W value for non-xc7 2020-01-14 11:34:40 -08:00
Eddie Hung a901a5fb44 print_stats footer to return peak memory, option for including children 2020-01-14 11:25:23 -08:00
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung de969adcd8 autoname: do not autoname ports 2020-01-14 10:13:29 -08:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung f63f76c372 read_aiger: also rename "$0" 2020-01-14 09:01:53 -08:00
Eddie Hung 531fddf797 abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc 2020-01-13 23:42:27 -08:00
Eddie Hung b678b15c6d abc9_ops: ignore inouts of all cell outputs for topo ordering 2020-01-13 23:33:37 -08:00
Eddie Hung eb7dd7d374 write_xaiger: fix case of PI and CI and (* keep *) 2020-01-13 23:23:21 -08:00
Eddie Hung 2c65e1abac abc9: break SCC by setting (* keep *) on output wires 2020-01-13 21:45:27 -08:00
Eddie Hung ee95fa959a read_aiger: uniquify wires with $aiger<autoidx> prefix 2020-01-13 21:28:27 -08:00
Eddie Hung 565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung a2c4d98da7 abc9: add -run option 2020-01-13 19:22:23 -08:00
Eddie Hung a6d4ea7463 abc9: respect (* keep *) on cells 2020-01-13 19:21:11 -08:00
Eddie Hung 9ec948f396 write_xaiger: add support and test for (* keep *) on wires 2020-01-13 19:07:55 -08:00
Eddie Hung 766e16b525 read_aiger: make $and/$not/$lut the prefix not suffix 2020-01-13 17:34:37 -08:00
Eddie Hung 0d2c06ee47 write_xaiger: cache arrival times 2020-01-13 09:50:50 -08:00
Eddie Hung 808b388e34 abc9: log which module is being operated on 2020-01-13 09:43:57 -08:00
Eddie Hung 9f3cb981d7 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-13 09:22:42 -08:00
Eddie Hung ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung 0f489c5ea3
Merge pull request #1627 from YosysHQ/eddie/fix1626 
synth_ice40: -abc2 to always use `abc` even if `-abc9`
 2020-01-13 08:17:34 -08:00
Marcin Kościelnicki 55f86eda36 edif: Just ignore connections to 'z 
Connecting a const 'z to a net should be equivalent to not connecting it
at all, so let's just ignore such connections on output.
 2020-01-13 14:49:31 +01:00
Eddie Hung ae619ba87a Add #1626 testcase 2020-01-12 15:21:26 -08:00
Eddie Hung c0b55deb0b synth_ice40: -abc2 to always use `abc` even if `-abc9` 2020-01-12 11:26:05 -08:00
Eddie Hung 35e49fde4d Another conflict 2020-01-11 18:57:25 -08:00
Eddie Hung 295e241c07 cleanup 2020-01-11 17:28:24 -08:00
Eddie Hung 7fa1b61aed Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-11 17:28:20 -08:00
Eddie Hung 79db12f238 Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-11 17:26:25 -08:00
Eddie Hung 58ab9f6021 write_xaiger: create holes_sigmap before modifications 2020-01-11 17:25:32 -08:00
Eddie Hung 556ed0e18a MIssed this merge conflict 2020-01-11 17:05:30 -08:00
Eddie Hung c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Eddie Hung 11128dccb5 Merge branch 'eddie/abc9_refactor' of github.com:YosysHQ/yosys into eddie/abc9_refactor 2020-01-11 13:56:41 -08:00