riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1639 from YosysHQ/eddie/fix_read_xaiger 

read_aiger: $lut prefix in front
This commit is contained in:
Eddie Hung 2020-01-15 16:22:49 -08:00 committed by GitHub
parent abba1541bc 5918ede9bd
commit 2bda51ac34
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 14 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/aiger/aigerparse.cc
View File

@ -1001,9 +1001,9 @@ void AigerReader::post_process()
if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit();
if (y_port.wire->width == 1)
module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
else
module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
}
}

12
tests/techmap/abc9.ys
View File

@ -38,3 +38,15 @@ abc9 -lut 4
design -load gold
scratchpad -copy abc9.script.flow3 abc9.script
abc9 -lut 4
design -reset
read_verilog -icells <<EOT
module top(input a, b, output o);
assign o = ~(a & b);
endmodule
EOT
abc9 -lut 4
clean
select -assert-count 1 t:$lut
select -assert-none t:$lut t:* %D