riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,270 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

2697 Commits

Author SHA1 Message Date
Eddie Hung c40b1aae42 Restore abc9 -keepff 2020-01-01 08:34:43 -08:00
Eddie Hung ac808c5e2a attributes.count() -> get_bool_attribute() 2020-01-01 08:33:32 -08:00
Eddie Hung 96db05aaef parse_xaiger to not take box_lookup 2019-12-31 17:06:03 -08:00
Eddie Hung cac7f5d82e Do not re-order carry chain ports, just precompute iteration order 2019-12-31 16:12:40 -08:00
Eddie Hung 4c3f517425 Remove delay targets doc 2019-12-30 16:11:42 -08:00
Eddie Hung 0735572934 write_xaiger to use scratchpad for stats; cleanup abc9 2019-12-30 15:35:33 -08:00
Eddie Hung fc4b8b8991 Remove submod changes 2019-12-30 14:56:14 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Eddie Hung d7ada66497 Add "synth_xilinx -dff" option, cleanup abc9 2019-12-30 14:13:16 -08:00
Eddie Hung 52a27700e2 Grammar 2019-12-30 12:26:39 -08:00
Miodrag Milanovic 3e14ff1667 fixed invalid char 2019-12-25 20:38:48 +01:00
Marcin Kościelnicki a24596def3 iopadmap: Emit tristate buffers with const OE for some edge cases. 2019-12-25 17:37:58 +01:00
Marcin Kościelnicki e226a8f7f1 Minor nit fixes 2019-12-25 15:39:40 +01:00
Eddie Hung 1d0ac659ad Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too 2019-12-23 14:40:59 -08:00
Eddie Hung 75acaff6f5 Fix CEA/CEB check 2019-12-23 14:22:13 -08:00
Eddie Hung edabe73377 Fix checking CE[AB] and for direct connections 2019-12-23 13:41:26 -08:00
Eddie Hung 71cac30309 Support unregistered cascades for A and B inputs 2019-12-23 12:38:18 -08:00
Eddie Hung d00533eaa8 Add DSP48A* PCOUT -> PCIN cascade support 2019-12-23 11:42:46 -08:00
Eddie Hung 509070f82f Disable clock domain partitioning in Yosys pass, let ABC do it 2019-12-23 08:36:20 -08:00
Marcin Kościelnicki 666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut 
Interpret "abc9 -lut" as lut string only if [0-9:]
 2019-12-20 13:09:00 -08:00
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung 269ba56a6d
Merge pull request #1581 from YosysHQ/clifford/fix1565 
Fix sim for assignments with lhs<rhs size
 2019-12-19 12:24:27 -05:00
Eddie Hung 3b559de6e9 Interpret "abc9 -lut" as lut string only if [0-9:] 2019-12-18 12:21:12 -08:00
Eddie Hung d0afe4e10d Merge branch 'master' of github.com:YosysHQ/yosys 2019-12-18 12:08:38 -08:00
Eddie Hung b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
N. Engelhardt 3671ecc7d0 use extra_args 2019-12-18 12:30:30 +01:00
Eddie Hung c9c77a90b3 Remove &verify -s 2019-12-17 16:11:54 -08:00
Eddie Hung b1b99e421e Use pool<> instead of std::set<> to preserver ordering 2019-12-17 16:10:40 -08:00
Clifford Wolf 41ed6ca7a5 Fix sim for assignments with lhs<rhs size, fixes #1565 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-12-17 17:36:30 +01:00
Eddie Hung dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung 33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung d9bf7061cd Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop 2019-12-16 16:49:48 -08:00
Eddie Hung 187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung 4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung 6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung 503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Eddie Hung 952d62991f Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr 2019-12-16 12:07:49 -08:00
Diego H 87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
N. Engelhardt abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Alyssa Milburn e709fd3da1 Fix opt_expr.eqneq.cmpzero debug print 2019-12-15 20:40:38 +01:00
Diego H 266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
N. Engelhardt ce3615b367 add periods and newlines to help message 2019-12-13 10:28:34 +01:00
Eddie Hung bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
N. Engelhardt 4c7cda1c8b add a command to read/modify scratchpad contents 2019-12-12 16:25:03 +01:00