riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,303 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

12303 Commits

Author SHA1 Message Date
Patrick Urban c244a7161b gatemate: Fix SDP read behavior 2023-05-30 09:05:43 +02:00
github-actions[bot] 43b807fe6f Bump version 2023-05-30 00:17:12 +00:00
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
github-actions[bot] 8596c5ce49 Bump version 2023-05-26 00:15:52 +00:00
Lofty cac1bc6fbe intel_alm: enable M10K initialisation 2023-05-25 18:56:34 +01:00
Eddie Hung ec8d7b1c68 abc9_ops -prep_hier to unmap entire module 2023-05-25 18:42:08 +01:00
Eddie Hung 862631d657 Add ABC9 DSP cascade test 2023-05-25 18:42:08 +01:00
Lofty 00b0e850db intel_alm: re-enable carry chains for ABC9 2023-05-25 18:28:10 +01:00
gatecat 52c8c28d2c Add recover_names pass to recover names post-mapping 2023-05-25 10:55:07 +02:00
github-actions[bot] 57c9eb70fe Bump version 2023-05-24 00:15:32 +00:00
Miodrag Milanović 5e36effe3c
Merge pull request #3777 from YosysHQ/micko/vhdl_verific 
Fix importing parametrized VHDL entity
 2023-05-23 11:44:49 +02:00
Miodrag Milanovic ecd289c100 Fix importing parametrized VHDL entity 2023-05-23 08:25:08 +02:00
Jannis Harder 4f3d1be96a
Merge pull request #3767 from YosysHQ/krys/yw_fix 
Assign wires an smtoffset
 2023-05-22 16:10:55 +02:00
Jannis Harder 5fb1223861
Merge pull request #3733 from AdamHillier/aiger-inputs 
Add outputs before inputs to the sigmap in the AIGER backend.
 2023-05-22 16:09:15 +02:00
N. Engelhardt 890849447f
Merge pull request #3716 from antmicro/kr/brackets 2023-05-22 16:06:38 +02:00
github-actions[bot] cdeef5481c Bump version 2023-05-22 00:16:53 +00:00
CORRADI Quentin e7156c644d Standard compliance for tests/verilog/block_labels.ys 
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
 2023-05-21 16:38:14 -04:00
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs 
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
 2023-05-18 16:50:11 +02:00
Jannis Harder e6f3914800 smt2: Use smt bv offset for `$any*`'s smtoffset 
While not setting the smtoffset here was clearly a bug, I think using
`chunk.offset` only worked incidentally. The `smtoffset` is an offset
into the `smtname, smtid` pair (here `"", idcounter`) which corresponds
to the smt bitvector `stringf("%s#%d", get_id(module), idcounter)` which
contains all the chunks this loop is iterating over.

Thus using an incrementing `smtoffset` (like the `$ff`/`$dff` case above
already does) should be the correct fix.
 2023-05-18 11:58:09 +02:00
github-actions[bot] 147cceb516 Bump version 2023-05-18 00:15:34 +00:00
Krystine Sherwin 52ad7a47f3
Assign wires an smtoffset 
Wires weren't being assigned an smtoffset value so when generating a yosys witness trace it would also use an offset of 0.
Not sure if this has any other effects, but it fixes the bug I was having.
@jix could you take a look at this?
 2023-05-18 10:37:55 +12:00
Miodrag Milanovic c2285b3460 fix file rights 2023-05-17 13:39:57 +02:00
Miodrag Milanović 07e76fcaca
Merge pull request #3751 from RTLWorks/main/issue2525 
[YOSYS-2525] fix read_liberty newline handling #2525
 2023-05-17 13:33:34 +02:00
Muthiah Annamalai (முத்து அண்ணாமலை) 693c609eec
Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
Muthu Annamalai 665e0f6131 remove new line per maintainer request 2023-05-17 04:20:13 +00:00
Miodrag Milanović acfdc5cc42
Merge pull request #3755 from RTLWorks/muthu/issue3498 
[YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style
 2023-05-15 16:34:35 +02:00
Kamil Rakoczy 6b3e6d96a3 Fix missing brackets around else 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2023-05-10 08:09:11 +02:00
github-actions[bot] d82bae32be Bump version 2023-05-10 00:15:03 +00:00
Muthiah Annamalai (முத்து அண்ணாமலை) c855502bd5
Update passes/techmap/libparse.cc 
Allow Liberty canonical identifier including double quotes in if-body and pass-through for Synopsys-style unquoted identifiers issue#3498

Co-authored-by: Aki <201479+lethalbit@users.noreply.github.com>
 2023-05-09 06:40:21 -07:00
Miodrag Milanović 7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script 
gowin: Add all the primitives.
 2023-05-09 11:13:51 +02:00
Miodrag Milanović 5c7cc6ff06
Merge pull request #3745 from rfuest/gowin_alu 
gowin: Fix X output of $alu techmap
 2023-05-09 11:12:50 +02:00
Miodrag Milanović 226a224640
Merge pull request #3749 from lethalbit/aki/plugin-stuff 
Updated the `plugin` command to better handle paths
 2023-05-09 08:46:02 +02:00
Miodrag Milanovic f790e00478 Next dev cycle 2023-05-09 08:00:06 +02:00
Miodrag Milanovic 9c5a60eb20 Release version 0.29 2023-05-09 07:57:55 +02:00
github-actions[bot] 0469405abf Bump version 2023-05-09 00:15:34 +00:00
N. Engelhardt 266036c6f9
Merge pull request #3756 from YosysHQ/krys/sim_writeback 2023-05-08 16:21:24 +02:00
N. Engelhardt 0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
N. Engelhardt ec56e625f4
Merge pull request #3742 from jix/fix_rename_witness_cell_renames 2023-05-08 16:13:28 +02:00
Krystine Sherwin 5a4e72f57a
Fix sim writeback check for yw_cosim 
Writeback of simulation state into initial state was only working for `run()` and `run_cosim_fst()`.
This change moves the writeback into the `write_output_files()` function so that all simulation modes work with the writeback option.
 2023-05-08 13:13:09 +12:00
Muthu Annamalai 17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest 2023-05-06 23:37:47 -07:00
YRabbit 8341fd450e Merge branch 'master' into all-primitives-script 2023-05-07 05:58:35 +10:00
Miodrag Milanović 4251d37f4f
Merge pull request #3610 from YosysHQ/synthprop 
Synthesizable properties
 2023-05-05 11:03:09 +02:00
Muthu Annamalai d2f3251528 adding unittest 2023-05-04 22:43:04 -07:00
Muthu Annamalai 81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525 
- newlines can be allowed in function parsing
 2023-05-04 22:30:27 -07:00
YRabbit 4f6a66e257 Merge branch 'master' into all-primitives-script 2023-05-05 10:21:50 +10:00
github-actions[bot] f93671eb85 Bump version 2023-05-05 00:15:06 +00:00
Jannis Harder 32f5fca2aa
Merge pull request #3694 from daglem/struct-attributes 
Handling of attributes for struct / union variables
 2023-05-04 22:15:10 +02:00
Dag Lem fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv 2023-05-04 14:28:21 +02:00
Dag Lem ad437c178d Handling of attributes for struct / union variables 
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.

(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.

Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."

    always_ff @(posedge clk) begin
        if (rotate) begin
            { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };

            if (res) begin
                v0.bytes <= '0;
            end else if (w) begin
                v0.bytes[addr] <= data;
            end
        end
    end
 2023-05-03 18:44:07 +02:00
Aki Van Ness bb240665b7
plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support 2023-05-03 03:35:55 -04:00