riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #3767 from YosysHQ/krys/yw_fix 

Assign wires an smtoffset
This commit is contained in:
Jannis Harder 2023-05-22 16:10:55 +02:00 committed by GitHub
parent 5fb1223861 ad2b04d63a
commit 4f3d1be96a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
backends/smt2/smt2.cc
View File

@ -626,9 +626,12 @@ struct Smt2Worker
}
bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
for (auto chunk : cell->getPort(QY).chunks())
int smtoffset = 0;
for (auto chunk : cell->getPort(QY).chunks()) {
if (chunk.is_wire())
decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire));
decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset));
smtoffset += chunk.width;
}
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(QY)), log_signal(cell->getPort(QY)));
if (cell->type == ID($anyseq))

3
passes/sat/sim.cc
View File

@ -223,7 +223,8 @@ struct SimInstance
if (wire->port_input && instance != nullptr && parent != nullptr) {
for (int i = 0; i < GetSize(sig); i++) {
in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i]));
if (instance->hasPort(wire->name))
in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i]));
}
}
}