35990b95ec
Extend support for format strings in Verilog front-end
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
e86ba3b94d
Make mask-and-shift the default for bitselwrite
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
...
This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
...
ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
...
Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
...
support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
...
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
...
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
...
ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
...
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
...
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663
...
verilog: instead of modifying localparam size, extend init constant expr
2020-03-03 08:34:31 -08:00
825b96fdcf
Comment out log()
2020-02-27 16:53:49 -08:00
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
...
Enum support
2020-02-20 18:17:25 +01:00
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
d12ba42a74
add attributes for enumerated values in ilang
...
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
c34d7b13f4
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
...
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
da485dc007
Modified $readmem[hb] to use '\' or '/' according the OS
...
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
fc33287bc1
verilog: instead of modifying localparam size, extend init constant expr
2020-02-05 17:19:42 -08:00
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
...
Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
...
As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
...
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
22c967e35e
ast: Add support for $sformatf system function
...
Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
...
The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
...
I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
1ac1697e15
Stray log_dump
2019-12-11 16:59:00 -08:00
af36943cb9
Preserve size of $genval$-s in for loops
2019-12-11 16:52:37 -08:00
e46e8753c8
frontends/ast: code style
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:55:43 +01:00
5501d9090a
sv: Fix typedefs in blocks
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:45 +01:00
af25585170
sv: Add support for memories of a typedef
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
30d2326030
sv: Add support for memory typedefs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
e70e4afb60
sv: Fix typedefs in packages
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
c962951612
sv: Fix typedef parameters
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
f6b5e47e40
sv: Switch parser to glr, prep for typedef
...
Signed-off-by: David Shah <dave@ds0.me>
2019-10-03 09:54:14 +01:00
25b08b1afd
Fix handling of range selects on loop variables, fixes #1372
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-16 11:25:37 +02:00
25e5fbac90
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
...
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-02 22:56:38 +02:00
fe1b2337fd
Do not propagate mem2reg attribute through to result
2019-08-22 16:57:59 -07:00
a6776ee35e
mem2reg to preserve user attributes and src
2019-08-21 13:36:01 -07:00
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
ee7c970367
IdString::str().substr() -> IdString::substr()
2019-08-06 19:08:33 -07:00
f1f5b4e375
Fix handling of functions/tasks without top-level begin-end block, fixes #1231
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 18:06:14 +02:00
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
59d74a3348
Re-enable "final loop assignment" feature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
e35fe1344d
Disabled "final loop assignment" feature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
4ad0ea5c3c
Determine correct signedness and expression width in for loop unrolling, fixes #370
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
638be461c3
Fix mem2reg handling of memories with upto data ports, fixes #888
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:21:17 +01:00
a5f4b83637
fix local name resolution in prefix constructs
2019-03-18 20:43:20 -04:00
d25a0c8ade
Improve handling of memories used in mem index expressions on LHS of an assignment
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
a4ddc569b4
Remove outdated "blocking assignment to memory" warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:10:55 +01:00
ab5b50ae3c
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:09:47 +01:00
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels
...
Add support for using SVA labels in yosys-smtbmc console output
2019-03-09 11:14:57 -08:00
a330c68363
Fix handling of task output ports in clocked always blocks, fixes #857
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
22ff60850e
Add support for SVA labels in read_verilog
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
ce6695e22c
Fix $global_clock handling vs autowire
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 10:38:13 -08:00
5d93dcce86
Fix $readmem[hb] for mem2reg memories, fixes #785
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 09:58:20 -08:00
7cfae2c52f
Use mem2reg on memories that only have constant-index write ports
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 13:35:09 -08:00
1816fe06af
Fix handling of defparam for when default_nettype is none
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
974927adcf
Fix handling of expression width in $past, fixes #810
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
fdf7c42181
Fix segfault in AST simplify
...
(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
86ce43999e
Make return value of $clog2 signed
...
As per Verilog 2005 - 17.11.1.
Fixes #708
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-24 18:49:23 +01:00
64e0582c29
Various indenting fixes in AST front-end (mostly space vs tab issues)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
39f891aebc
Make and dependent upon LSB only
2018-11-03 13:39:32 -04:00
d86ea6badd
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
...
Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error
...
Fix issue #630
2018-10-17 12:13:18 +02:00
75009ada3c
Synthesis support for SystemVerilog interfaces
...
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
62424ef3de
Add read_verilog $changed support
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
9f9fe94b35
Fix handling of $past 2nd argument in read_verilog
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-30 18:43:35 +02:00
80a07652f2
Fixed issue #630 by fixing a minor typo in the previous commit
...
(as well as a non critical minor code optimization)
2018-09-25 00:32:57 +03:00
c693f595c5
Merge branch 'master' into pr_reg_wire_error
2018-09-18 01:27:01 +03:00
f6fe73b31f
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
...
on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error
...
Fix remaining log_file_error(); emit dependent file references in new…
2018-08-15 14:01:34 +02:00
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
...
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
3101b9b8c9
Fix remaining log_file_error(); emit dependent file references in new line.
...
There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
2018-07-20 18:52:52 -07:00
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
...
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
...
Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
73d426bc87
Modified errors into warnings
...
No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
...
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Claire Wolf
David Shah
whitequark
Jeff Wang
Eddie Hung
Claire Wolf
huaixv
Alberto Gonzalez
Rodrigo Alejandro Melo
Rodrigo Alejandro Melo
Zachary Snow
Sylvain Munaut
ZipCPU
Ruben Undheim
Dan Gisselquist
Udi Finkelstein
Henner Zeller