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14201 Commits

Author SHA1 Message Date
Johann Glaser 278085fa01 added log_header to miter and expose pass, show cell type for exposed ports 2014-05-28 18:05:38 +02:00
Johann Glaser 63dfbb18cf new flags -ignore_miss_func and -ignore_miss_dir for read_liberty 2014-05-28 16:50:13 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf 68c059565a Fixed bug in opt_reduce (see vloghammer issue_044) 2014-05-12 12:45:47 +02:00
Clifford Wolf f69b5800c9 fixed syntax error in dot file created by "show" command 2014-05-10 16:22:56 +02:00
Clifford Wolf 973959c7ea Merge branch 'master' of github.com:cliffordwolf/yosys 2014-05-09 18:24:13 +02:00
Clifford Wolf bfd62268cc Updated ABC to 67c84cdd49e4 2014-05-09 18:23:21 +02:00
Clifford Wolf 51a615b26d Progress in presentation 2014-05-06 14:42:04 +02:00
Clifford Wolf 30774ec6bc Improved ezsat stand-alone tests 2014-05-06 13:48:25 +02:00
Clifford Wolf a5a519a9d1 workaround for OpenBSD 'stdout' implementation 2014-05-03 12:55:56 +02:00
Clifford Wolf 75a5d6bd1e workaround for OpenBSD 'stdin' implementation 2014-05-02 13:22:26 +02:00
Clifford Wolf f7e9056a93 Merge pull request #35 from bentley/dox 
Typos and grammar fixes through chapter 4.
 2014-05-02 13:18:43 +02:00
Anthony J. Bentley 154c9f8b51 Typos and grammar fixes through chapter 4. 2014-05-02 03:08:40 -06:00
Clifford Wolf 7188542155 Fixed clang -Wdeprecated-register warnings 2014-04-20 14:28:23 +02:00
Clifford Wolf a1be4816d6 Replaced depricated %name-prefix= bison directive 2014-04-20 14:22:11 +02:00
Clifford Wolf d2d48996c4 minisat compile fix 2014-04-20 14:17:40 +02:00
Clifford Wolf 12a3c05229 Updated README 2014-04-18 10:19:46 +02:00
Clifford Wolf d18c10d991 Merge pull request #33 from bentley/dox 
Typos and grammar fixes through chapter 2.
 2014-04-11 13:06:02 +02:00
Anthony J. Bentley 9c1e578afe Typos and grammar fixes through chapter 2. 2014-04-11 02:42:59 -06:00
Clifford Wolf 6ef2224331 Merge pull request #31 from bentley/posix-rm 
Remove non-POSIX 'rm -v'.
 2014-04-05 02:56:28 +02:00
Anthony J. Bentley 66a5da5edc POSIX find requires a path argument. 2014-04-04 16:51:27 -06:00
Anthony J. Bentley b950197da1 Remove non-POSIX 'rm -v'. 2014-04-04 16:39:03 -06:00
Clifford Wolf 7370ae01e9 Added SIMLIB_NOLUT to simlib.v 2014-04-02 21:28:33 +02:00
Clifford Wolf e24797add0 Added SIMLIB_NOSR to simlib.v 2014-04-02 21:06:55 +02:00
Clifford Wolf d4a1b0af5b Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
Clifford Wolf a3b9692a68 Fixed mapping of Verific WIDE_DFFRS operator 2014-03-20 13:40:01 +01:00
Clifford Wolf 470c2455e4 Fixed mapping of Verific FADD primitive with unconnected outputs 2014-03-20 13:26:52 +01:00
Clifford Wolf 9a34486bfb Fixed performance problem in opt_mux with nets driven by many conflicting drivers 2014-03-19 10:05:01 +01:00
Clifford Wolf cdf1257565 Progress in Verific bindings 2014-03-17 14:43:16 +01:00
Clifford Wolf e164edc8d1 Fixed typo in RTLIL::Module::addAdff() 2014-03-17 14:41:41 +01:00
Clifford Wolf 0b0dcfda7d Progress in Verific bindings 2014-03-17 02:43:53 +01:00
Clifford Wolf a67cd2d4a2 Progress in Verific bindings 2014-03-17 01:56:00 +01:00
Clifford Wolf acda74c12c Added support for memories to verific bindings 2014-03-16 17:05:05 +01:00
Clifford Wolf 7545510edc Use Verific Net::{IsGnd,IsPwr} API in Verific bindings 2014-03-16 16:06:03 +01:00
Clifford Wolf ef1795a1e8 Fixed typo in RTLIL::Module::{addSshl,addSshr} 2014-03-15 22:52:10 +01:00
Clifford Wolf 0ebee4c8e7 Progress in Verific bindings 2014-03-15 22:51:12 +01:00
Clifford Wolf fc2c821407 Progress in Verific bindings 2014-03-15 15:31:54 +01:00
Clifford Wolf 1d00ad9d4d Progress in Verific bindings 2014-03-15 14:36:11 +01:00
Clifford Wolf b7c71d92f6 Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API 2014-03-15 14:35:29 +01:00
Clifford Wolf e37d672ae7 Progress in Verific bindings 2014-03-14 16:40:25 +01:00
Clifford Wolf 5da9558fa8 Added log_dump() support for generic pointers 2014-03-14 16:39:50 +01:00
Clifford Wolf 0ac915a757 Progress in Verific bindings 2014-03-14 11:46:13 +01:00
Clifford Wolf 77e5968323 Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API 2014-03-14 11:45:44 +01:00
Clifford Wolf 9a1accf692 Progress in Verific bindings 2014-03-13 18:21:00 +01:00
Clifford Wolf 6a53bc7b27 Copy Verific vdbs files to Yosys "share" data directory 2014-03-13 17:34:31 +01:00
Clifford Wolf 34e54cda5b Small improvement in SAT log messages 2014-03-13 13:12:49 +01:00
Clifford Wolf 7a1ac11203 Added test_navre.ys for verific frontend 2014-03-13 13:12:06 +01:00
Clifford Wolf 542afc562f Hotfix for kernel/compatibility.h 2014-03-13 12:55:15 +01:00
Clifford Wolf 0e658dbc02 Merge branch 'master' of https://github.com/Siesh1oo/yosys 2014-03-13 12:50:34 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00