Commit Graph

107 Commits

Author SHA1 Message Date
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Marcelina Kościelnicka 9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Marcelina Kościelnicka 8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Fixes #2962.
2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka 24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Zachary Snow c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
Marcelina Kościelnicka a0e912ba99 proc: Run opt_expr at the end 2021-07-27 20:44:45 +02:00
Rupert Swarbrick 88f20fa4dd Delete unused found_init variable
Spotted during compilation:

    passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
    passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
2021-07-14 10:19:07 +01:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
2021-07-12 00:47:34 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka a55bf6375b proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
2021-03-15 17:17:29 +01:00
Marcelina Kościelnicka 4e03865d5b Add support for memory writes in processes. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka 760284033d proc_dff: Fix emitted FF when a register is not assigned in async reset
Fixes #2619.
2021-03-08 17:01:43 +01:00
Marcelina Kościelnicka d245e2bae5 proc_clean: Fix empty case removal conditions.
Fixes #2639.
2021-03-06 17:39:50 +01:00
Peder Bergebakken Sundt 656ee70f8e proc: Add -nomux switch
running proc -nomux will ommit the proc_mux pass
2020-08-20 22:58:08 +02:00
Marcelina Kościelnicka 557f81cb49 proc_dlatch: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka b33744b03a proc_dlatch: Remove init values for combinatorial processes.
Fixes #2258.
2020-07-12 18:50:30 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
David Shah ca99b1ee8d proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:46:41 +00:00
whitequark 4a942ba7b9 proc_clean: fix order of switch insertion.
Fixes #1268.
2019-08-19 16:44:23 +00:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
whitequark 0b09a347dc proc_prune: fix handling of exactly identical assigns.
Before this commit, in a process like:
   process $proc$bug.v:8$3
     assign $foo \bar
     switch \sel
       case 1'1
         assign $foo 1'1
         assign $foo 1'1
       case
         assign $foo 1'0
     end
   end
both of the "assign $foo 1'1" would incorrectly be removed.

Fixes #1243.
2019-08-08 05:32:35 +00:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Jean-François Nguyen 320bf2fde5 proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
Clifford Wolf e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
A new proc_prune pass
2019-07-09 16:59:18 +02:00
whitequark 44bcb7a187 proc_prune: promote assigns to module connections when legal.
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark 5fe0ffe30f proc_prune: new pass.
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark f7a14a5678 proc_clean: add -quiet option.
This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
whitequark 48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
Clifford Wolf 88be1cbfa5 Improve proc full_case detection and handling, fixes #931
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 15:13:47 +02:00
Eddie Hung 4da4a6da2f Revert #895 2019-04-16 11:07:51 -07:00
Eddie Hung b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung adc6efb584 Recognise default entry in case even if all cases covered (#931) 2019-04-11 12:34:51 -07:00
Sylvain Munaut 39380c45ba proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-04-03 14:50:12 +02:00
Eddie Hung b7a3d35c6b Create one $shiftx per bit in width 2019-03-25 11:16:56 -07:00
Eddie Hung 2507d01b03 Add a pmux-to-shiftx optimisation to proc_mux 2019-03-23 16:45:36 -07:00
whitequark 58d059ccb7 proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
whitequark 95b6c35882 proc_clean: fix fully def check to consider compare/signal length.
Fixes #790.
2019-01-18 23:22:19 +00:00
whitequark 18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00
whitequark b784440857 proc_clean: remove any empty cases at the end of the switch.
Previously, only completely empty switches were removed.
2018-12-22 09:04:46 +00:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf ca2adc30c9 Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
Clifford Wolf f9d023c53f Add src attribute to extra cells generated by proc_dlatch 2017-09-09 10:18:08 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf 2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00