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10,257 Commits 81 Branches 48 Tags 63 MiB
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145 Commits

Author SHA1 Message Date
Clifford Wolf 406f86a91e Added realexpr.v test case 2014-06-14 12:01:17 +02:00
Clifford Wolf 3af7c69d1e added tests for new verilog features 2014-06-07 12:26:11 +02:00
Clifford Wolf c82db39935 Added tests/simple/repwhile.v 2014-06-06 17:47:20 +02:00
Clifford Wolf a67cd2d4a2 Progress in Verific bindings 2014-03-17 01:56:00 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf 4df7e03ec9 Bugfix in name resolution with generate blocks 2014-01-30 15:01:28 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf ecc30255ba Added proper === and !== support in constant expressions 2013-12-27 13:50:08 +01:00
Clifford Wolf 994c83db01 Added multiplier test case from eda playground 2013-12-18 13:43:53 +01:00
Clifford Wolf fbd06a1afc Added elsif preproc support 2013-12-18 13:41:36 +01:00
Clifford Wolf 921064c200 Added support for macro arguments 2013-12-18 13:21:02 +01:00
Clifford Wolf 4a4a3fc337 Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf a2d053694b Fix in sincos testbench gen 2013-12-04 09:24:52 +01:00
Clifford Wolf d1517b7982 Added sincos test case 2013-12-04 09:10:41 +01:00
Clifford Wolf 609caa23b5 Implemented correct handling of signed module parameters 2013-11-24 17:17:21 +01:00
Clifford Wolf 1e6836933d Added modelsim support to autotest 2013-11-24 15:10:43 +01:00
Clifford Wolf 65ad556f3d Another name resolution bugfix for generate blocks 2013-11-20 13:57:40 +01:00
Clifford Wolf 92035fb38e Implemented indexed part selects 2013-11-20 13:05:27 +01:00
Clifford Wolf 19dba2561e Implemented part/bit select on memory read 2013-11-20 10:51:32 +01:00
Clifford Wolf c5e26f839c Added additional mem2reg testcase 2013-11-18 19:55:39 +01:00
Clifford Wolf 2a25e3bca3 Fixed parsing of default cases when not last case 2013-11-18 16:10:50 +01:00
Clifford Wolf fc6dc0d7b8 Fixed handling of power operator 2013-11-07 22:20:00 +01:00
Clifford Wolf ada80545fa Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes) 2013-11-02 21:13:01 +01:00
Clifford Wolf 943329c1dc Various ast changes for early expression width detection (prep for constfold fixes) 2013-11-02 13:00:17 +01:00
Clifford Wolf 628b994cf6 Added support for complex set-reset flip-flops in proc_dff 2013-10-24 16:54:05 +02:00
Clifford Wolf d61699843f Improved handling of dff with async resets 2013-10-21 14:51:58 +02:00
Clifford Wolf 759852914d Added support for "2**n" shifter encoding 2013-08-12 14:47:50 +02:00
Clifford Wolf c8763301b4 Added $div and $mod technology mapping 2013-08-09 17:09:24 +02:00
Clifford Wolf 3650fd7fbe More fixes in ternary op sign handling 2013-07-12 13:13:04 +02:00
Clifford Wolf ded769c98c Fixed sign handling in ternary operator 2013-07-12 01:15:37 +02:00
Clifford Wolf b380c8c790 Another vloghammer related bugfix 2013-07-11 19:24:59 +02:00
Clifford Wolf 5dab327b30 More fixes in ast expression sign/width handling 2013-07-09 23:41:43 +02:00
Clifford Wolf 618b2ac994 Merge branch 'master' of github.com:cliffordwolf/yosys 2013-07-09 19:00:10 +02:00
Clifford Wolf 7daeee340a Fixed shift ops with large right hand side 2013-07-09 18:59:59 +02:00
Clifford Wolf 00a6c1d9a5 Major redesign of expr width/sign detecion (verilog/ast frontend) 2013-07-09 14:31:57 +02:00
Clifford Wolf e8da3ea7b6 Fixed another bug found using vloghammer 2013-07-07 16:49:30 +02:00
Clifford Wolf 56432a920f Added defparam support to Verilog/AST frontend 2013-07-04 14:12:33 +02:00
Clifford Wolf e0c408cb4a Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values 2013-04-13 21:19:10 +02:00
Clifford Wolf 5640b7d607 Added test cases from 2012 paper on comparison of foss verilog synthesis tools 2013-03-31 11:17:56 +02:00
Clifford Wolf d9bc024d29 Renamed hansimem.v test case to mem_arst.v 2013-03-24 15:25:08 +01:00
Clifford Wolf c3c9e5a02f Added hansimem testcase (memory with async reset) 2013-03-24 10:40:40 +01:00
Johann Glaser 3cfbc18601 added ckeck for Icarus Verilog, otherwise the tests are silently stopped 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:15 +01:00
Clifford Wolf 2d9cbd3b02 added more .gitignore files (make test) 2013-01-05 11:35:52 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00