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7582 Commits

Author SHA1 Message Date
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Clifford Wolf 779ce3537f Add "write_aiger -L" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-18 13:33:02 +02:00
Clifford Wolf b88d2e5f30 Fix stupid bug in btor back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-18 11:56:14 +02:00
Clifford Wolf 36df37a734 Bump version 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 13:05:41 +02:00
Clifford Wolf 861f2af5aa
Merge pull request #1380 from YosysHQ/clifford/fix1372 
Fix handling of range selects on loop variables
 2019-09-16 13:05:02 +02:00
Clifford Wolf 25b08b1afd Fix handling of range selects on loop variables, fixes #1372 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 11:25:37 +02:00
Eddie Hung 2b93b8fc74
Merge pull request #1374 from YosysHQ/eddie/fix1371 
Fix two non-deterministic behaviours that cause divergence between compilers
 2019-09-15 13:56:07 -07:00
Marcin Kościelnicki 09ac36da60 xilinx: Make blackbox library family-dependent. 
Fixes #1246.
 2019-09-15 13:37:24 +02:00
Clifford Wolf d9f99745da
Merge pull request #1377 from YosysHQ/clifford/fixzdigit 
Fix handling of z_digit "?" and fix optimization of cmp with "z"
 2019-09-15 11:04:31 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Eddie Hung f492567c87 Oops 2019-09-13 18:19:07 -07:00
Eddie Hung 681be20ca2 Add `undef DSP48E1_INST 2019-09-13 17:07:18 -07:00
Eddie Hung a2eee9ebef Add counter-example from @cliffordwolf 2019-09-13 16:41:10 -07:00
Eddie Hung 14d72c39c3 Revert "Make one check $shift(x)? only; change testcase to be 8b" 
This reverts commit e2c2d784c8.
 2019-09-13 16:33:18 -07:00
Eddie Hung 9a84e4711c Spacing 2019-09-13 16:30:44 -07:00
Eddie Hung 9a73adde50 Explicitly order function arguments 2019-09-13 16:18:05 -07:00
Eddie Hung 61877e1370 Fix D -> P{,COUT} delay 2019-09-13 13:32:55 -07:00
Eddie Hung d0b202c58d Add no MULT no DPORT config 2019-09-13 12:05:14 -07:00
Eddie Hung 247a63f55d Add support for MULT and DPORT 2019-09-13 11:45:55 -07:00
Eddie Hung 5473e597bf Use template specialisation 2019-09-13 11:13:57 -07:00
Eddie Hung 95e80809a5 Revert "SigSet<Cell*> to use stable compare class" 
This reverts commit 4ea34aaacd.
 2019-09-13 09:49:15 -07:00
Eddie Hung e235dd0785 Refine diagram 2019-09-13 09:34:40 -07:00
Clifford Wolf a67d63714b Fix handling of z_digit "?" and fix optimization of cmp with "z" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 13:39:39 +02:00
Clifford Wolf 4da6e19fe1
Merge pull request #1373 from YosysHQ/clifford/fix1364 
Fix lexing of integer literals
 2019-09-13 10:22:34 +02:00
Clifford Wolf 855e6a9b91 Fix lexing of integer literals without radix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-13 10:19:58 +02:00
Eddie Hung 734034a872 Add an ASCII drawing 2019-09-12 18:13:46 -07:00
Eddie Hung c52863f147 Finish explanation 2019-09-12 18:01:49 -07:00
Eddie Hung aaeaab4ac0 Rename to techmap_guard 2019-09-12 17:45:02 -07:00
Eddie Hung 6bb8e6a726 Initial DSP48E1 box support 2019-09-12 17:11:01 -07:00
Eddie Hung 3a39073302 Set more ports explicitly 2019-09-12 17:10:43 -07:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
Eddie Hung c487a8ff25 Grammar 2019-09-12 12:00:34 -07:00
Eddie Hung c05a403dd1 static_assert to enforce this going forward 2019-09-12 11:45:17 -07:00
Eddie Hung 4ea34aaacd SigSet<Cell*> to use stable compare class 2019-09-12 11:45:02 -07:00
David Shah 6044fff074
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock 
Add equiv_opt -multiclock
 2019-09-12 12:26:28 +01:00
Clifford Wolf 7eb593829f Fix lexing of integer literals, fixes #1364 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-12 09:43:32 +02:00
Eddie Hung f3081c20e7 Add support for A1 and B1 registers 2019-09-11 17:16:46 -07:00
Eddie Hung 4369fc17d0 Raise a RuntimeError instead of AssertionError 2019-09-11 17:06:37 -07:00
Eddie Hung 7d644f40ed Add AREG=2 BREG=2 test 2019-09-11 17:05:47 -07:00
Eddie Hung 6fa6bf483c Rename {A,B} -> {A2,B2} 2019-09-11 16:21:24 -07:00
Eddie Hung 3a49aa6b4a Tidy up 2019-09-11 14:20:49 -07:00
Eddie Hung 817ac7c5e0 Fix UB 2019-09-11 14:18:02 -07:00
Eddie Hung 63431fe42a Fix UB 2019-09-11 14:17:45 -07:00
Eddie Hung 690b1a064d Add PCOUT -> PCIN non-shifted cascading 2019-09-11 13:48:45 -07:00
Eddie Hung c0f26c2da8 Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp 2019-09-11 13:37:11 -07:00
Eddie Hung bdb5e0f29c Cope with presence of reset muxes too 2019-09-11 13:36:37 -07:00
Eddie Hung 4937917cd8 Cleanup 2019-09-11 13:22:52 -07:00
Eddie Hung f46ef47893 Add more tests 2019-09-11 13:22:41 -07:00
Eddie Hung 0ebbecf833 Missing space 2019-09-11 13:06:59 -07:00
Eddie Hung e9eb855d38 Make unextend a udata 2019-09-11 13:06:49 -07:00